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@InProceedings{BastenHoogerbru01,
  title = "{E}fficient {E}xecution of {P}rocess {N}etworks",
  author= "Basten, T. and Hoogerbrugge, J.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "1--14",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Kahn process networks (KPNs) [1] are a popular modeling
     technique for media- and signal-processing applications. A
     KPN makes parallelism and commu-nication in an application
     explicit; thus, KPNs are a modeling paradigm that is very
     suitable for multi-processor architectures. We present
     techniques for the efficient ex-ecution of KPNs, taking into
     account both execution time and memory usage."
}
@InProceedings{MayMuller01,
  title = "{C}opying, {M}oving and {B}orrowing {S}emantics",
  author= "May, David and Muller, Henk",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "15--26",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "In this paper we discuss primitives for mobilising code and
     communications. We distinguish three types of semantics for
     mobility: copying (where an identical copy is created
     remotely), moving (where the original is destroyed), and
     borrowing (where the original is moved to the target and
     back to where it came from at defined moments). We discuss
     these semantics for mobile code and mobile channels. We have
     implemented Icarus, a language that uses borrowing semantics
     for mobile code (the on-statement) and moving semantics for
     mobile channels (first class channels)."
}
@InProceedings{Moore01,
  title = "{P}arallel {G}enetic {A}lgorithms to {F}ind {N}ear {O}ptimal {S}chedules for {T}asks on {M}ultiprocessor {A}rchitectures",
  author= "Moore, M.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "27--36",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Parallel genetic schedulers (PGS) are applied to a
     combinatorial optimisation problem, the scheduling of
     multiple, independent, non-identical tasks. The tasks are
     functionally partitioned and must be distributed over a
     multicomputer or multiprocessor system. As each task
     completes execution, a result message must be communicated.
     Communication occurs over a shared bus. This problem is
     known to be NP-complete [1]. The PGS execute on a shared
     memory multiprocessor system and on a simulated SIMD torus.
     Schedules produced by the PGS are compared to each other, to
     those found by an exponential-time optimal branch and bound
     algorithm, and to those found by a linear-time opportunistic
     algorithm. The PGS produce extremely accurate schedules very
     quickly. When the PGS are executed with increasing numbers
     of processors, near linear speedups are obtained with no
     decrease in the quality of the resulting schedules."
}
@InProceedings{TrigerONeill01,
  title = "{A}dapted {OS} {L}ink / {DS} {L}ink {P}rotocols for {U}se in {M}utliprocessor {R}outing {N}etworks",
  author= "Triger, S. and O'Neill, Brian C. and Clark, S.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "37--48",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Inter-processor communications play a vital role in the
     performance of distributed parallel networks. This document
     analyses various protocol options for high speed, serial,
     inter-processor communications for use in embedded
     multiprocessor systems. The protocol is used to pass
     information in a fault tolerant routing network. The work
     has resulted in a custom processor interface, which forms
     the gateway between the processing node and the distributed
     communications network, building on previous work. The role
     of the interface is to provide maximum hardware support for
     communications between the network and the processor. This
     alleviates the processor from having to oversee
     communications transactions and allows it to concentrate on
     program execution. The research focuses on protocol
     alterations aimed at improving the fault tolerant aspects of
     the design when dealing with various forms of network
     failure. By improving the fault tolerance of the network,
     communications bottlenecks can be avoided and data
     throughput can be maximised. Previously, communications
     across the network had used the OS Links protocol and,
     experimentally, DS Links. These were analysed and adapted to
     provide the current communications protocol, which is
     compared with these protocols. This protocol is more
     efficient, and helps to provide many features to ensure data
     integrity."
}
@InProceedings{Lawrence01a,
  title = "{S}uccesses and {F}ailures: {E}xtending {CSP}",
  author= "Lawrence, Adrian E.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "49--66",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Standard CSP, timed or untimed, does not include a general
     treatment of priority, although the PRI ALT constructor is
     an essential part of occam and hardware compilation
     languages based upon occam. This is a revised version of the
     original paper which introduced CSPP, an extension of CSP
     incorporating priority. CSPP is defined by a novel
     denotational semantics, Acceptances, based on Successes
     rather than the usual Failures. The idea is to characterise
     a process by what it successfully accepts, rather than by
     what it refuses to do. In the light of experience, it might
     better have been called 'Responses'. The original
     Acceptances was exploratory, and tried to avoid constraining
     the sorts of systems, particularly circuits, that could be
     described. Experience has shown that it can be substantially
     simplified at very little cost. A new notation makes it much
     easier to follow, especially for the non specialist. This
     revision of the original introduction presents the
     simplified CSPP while retaining most of the motivational
     material. It is intended to have something of a tutorial
     flavour: three other papers, are more condensed, and deal
     with more technical matters. But the core semantics is
     common to all four. CSPP provides a rigorous comprehensible
     and simple foundation for compositional hardware-software
     codesign. HCSP is a further extension which includes extra
     facilities needed to describe certain circuits. And a
     further radical extension lifts the usual restrictions of
     timed CSP, and describes continuous analogue phenomena. CSPP
     was first presented informally at the Twente WoTUG--20
     technical meeting."
}
@InProceedings{Lawrence01b,
  title = "{CSPP} and {E}vent {P}riority",
  author= "Lawrence, Adrian E.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "67--92",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "CSPP is an extension of CSP which includes priority as used
     in standard occam. The occam community has often discussed
     whether those notions are really adequate, a particular
     concern being the difficulties associated with priority
     inversion. One idea is to give priority to sets of events
     considered independently of the processes that perform them.
     We call this 'event priority'. Event priority is static in
     this presentation. But it is possible to handle dynamic
     priority using a global synchronisation when the 'event
     priority' changes. Obviously there is no problem for a
     software system with a central scheduler, but the theory
     here is addressing a far wider class of systems, in
     particular massively parallel, widely distributed,
     implemented in either hardware or software or both. It may
     be that some higher level of abstraction should replace
     priority: priority is a mechanism for achieving certain
     properties, often relating to time and limited resources.
     Here we content ourselves with finding a formal description
     of a language including event-priority."
}
@InProceedings{Lawrence01c,
  title = "{I}nfinite {T}races, {A}cceptances and {CSPP}",
  author= "Lawrence, Adrian E.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "93--102",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "There is a long standing problem when infinite traces are
     included in denotational semantic models of CSP. Full models
     fail to be Complete Partial Orders under refinement. This
     paper introduces a novel, but entirely natural, way of
     representing infinite behaviour in which refinement is a
     Complete Partial Order when the alphabet of events is
     finite. Acceptance semantics also solves the problem of
     infinite behaviour with an infinite alphabet. That requires
     a different construction based on a metric space and will be
     described elsewhere."
}
@InProceedings{TownerMay01,
  title = "{T}he `{U}niform {H}eterogeneous {M}ulti-{T}hreaded' {P}rocessor {A}rchitecture",
  author= "Towner, Daniel and May, David",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "103--116",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Multi-threaded processor architectures are capable of
     concurrently execut-ing multiple threads using a shared
     execution resource. Two of their advantages are their
     ability to hide latency within a thread, and their high
     execution efficiency. Un-fortunately, single thread
     performance is often poor. In this paper we present a simple
     model of a multi-threaded processor, and show how an
     occam-like language may be compiled into fine grained
     threads suitable for executing on this processor. These fine
     grained threads allow all but the most serial programs to be
     compiled into multiple threads. Thus, poor single thread
     performance is avoided by ensuring that sufficient threads
     are always available, even at the instruction level. We call
     this technique ‘uni-form heterogeneous multi-threading’
     (UHM). A compiler implementing UHM has been built, along
     with a cycle accurate simulator of a UHM processor. We
     demon-strate that the processor is capable of good
     performance, whilst being simple to design and build."
}
@InProceedings{RischelSun01,
  title = "{E}vent-{B}ased {D}esign of {C}oncurrent {P}rograms with {J}ava {I}mplementation",
  author= "Rischel, H. and Sun, H.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "117--128",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "A systematic design approach to safety-critical systems is
     introduced by means of the Production Cell case study. The
     design is documented using CSP-style processes, which allow
     verifications using formal techniques, as well as
     programming in Java using the JCSP library."
}
@InProceedings{VinterAnshus01,
  title = "{U}sing {T}wo-, {F}our- and {E}ight-{W}ay {M}ultiprocessors as {C}luster {C}omponents",
  author= "Vinter, Brian and Anshus, Otto J. and Larsen, Tore and Bjørndalen, John Markus",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "129--148",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "This work considers the pros and cons of different size SMPs
     as nodes in clusters. We investigate the Intel SMP
     architecture and consider the potential of and some problems
     with larger node-sizes in clusters of multiprocessors. Six
     applications that represent different classes of parallel
     applications are developed in versions that support both
     shared and distributed memory. Performance measurements are
     done on three different clusters of multiprocessors, with
     the purpose of identifying how the number of processors in
     each SMP node impacts the cluster performance. Our results
     show that clusters using higher order SMPs do not give a
     clear performance benefit compared to clusters using two-way
     SMPs. Off the bench mark-suite of six applications, the
     performance of two turn out to be independent of node-size,
     two show an advantage of larger node-sizes, as much as 34
     percent improvement of eight-way nodes over a dual-system,
     while the remaining two show an advantage of dual-processor
     nodes as big as 11 percent over an eight-way cluster."
}
@InProceedings{YangStiles01,
  title = "{G}uarenteed {M}essage {D}elivery {T}ime on {R}eal-{T}ime {D}istributed {S}ystems",
  author= "Yang, T. -Y. and Stiles, G. S.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "149--166",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "Real-time systems require guaranteed timely delivery of
     messages; failure to deliver a message on time may result in
     failure of the system and possible damage to life and
     property. We describe here an extension and implementation
     of an algorithm developed by Kandlur et al. for guaranteed
     message delivery. We extend this by adding two-phase
     randomized routing in the channel establishment procedure;
     this scheme requires each route to go first to a randomly
     chosen intermediate node, and only then to its actual
     destination. This scheme balances the load demonstrably
     better than direct routing, with respect to the likelihood
     of acceptance of each individual channel. Given certain
     constraints on the generation and size of messages, it is
     possible to schedule those messages such that messages
     arrive within their desired deadlines. Experiments on an
     8-node network demonstrate the feasibility of the approach,
     and provide verification of Kandlur's algorithm."
}
@InProceedings{WattMay01,
  title = "{A} {P}rogramming {L}anguage for {H}ardware/{S}oftware {C}o-{D}esign",
  author= "Watt, D. R. and May, David",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "167--178",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "We have developed a programming language that allows
     programs to be expressed as single specifications in which
     any number of processes may be tagged for hardware
     compilation and the rest are compiled into software. We
     introduce a number of novel transformations that may be
     arbitrarily applied to an occam process in order to
     decompose it into two semantically equivalent concurrent
     processes. Our compiler targets hardware by compiling one of
     these processes into a field programmable gate array and the
     other into x86 object code. Furthermore, the compiler
     integrates a specialised communications protocol between the
     two programs that consists of a full-duplex channel
     implementation, multiplexor and buffers that are dependent
     on the program structure and that guarantee all external
     communications are free from deadlock. We demonstrate the
     elegance of our language and the power of our compiler on a
     small benchmark program."
}
@InProceedings{Peel01,
  title = "{A} {R}econfigurable {H}ost {I}nterconnection {S}cheme for {O}ccam-{B}ased {F}ield {P}rogrammable {G}ate {A}rrays",
  author= "Peel, Roger M. A.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "179--192",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "This paper reports on the development of an interconnection
     scheme for field-programmable gate arrays (FPGAs). These
     FPGAs may be programmed in the Occam parallel programming
     language. Now, not only may the inter-process communication
     channels provided by Occam be used on-chip, but they may
     also be extended to a host processor using the ubiquitous
     Universal Serial Bus (USB). Bidirectional channels of BYTEs
     are carried along this bus to a host processor (running
     Linux) where they are presented to application code using a
     device driver that provides similar capabilities to the
     standard B004 card link driver. A unidirectional end-to-end
     throughput between Linux processes and FPGA processes,
     across USB, has been measured as high as 1025 kbytes/sec,
     although this rate is only achieved in favourable
     circumstances. Similarly, 410 kbytes/sec may be transferred
     in both directions simultaneously. Unidirectional
     transmission rates of more than 600 kbytes/sec, and
     bidirectional rates of 175-300 kbytes/sec in each direction
     may be achieved in a wide range of circumstances. The paper
     presents a range of performance figures, explaining which
     are limited by the underlying characteristics of the USB bus
     and which are caused by the current implementation. By
     implementing a transputer OS-Link in the FPGA, it is
     possible for a USB- enabled computer to communicate with a
     network of transputers, providing a convenient - and
     potentially faster - alternative to previous methods."
}
@InProceedings{McConnellWinser01,
  title = "{A} 40 {G}bit/s {N}etwork {P}rocessor {D}esign {P}latform",
  author= "McConnell, R. and Winser, P.",
  editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
  pages = "193--212",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
  isbn= "1 58603 202 X",
  year= "2001",
  month= "sep",
  abstract= "As the Internet evolves, the rapidly increasing demand for
     bandwidth is matched by a greater need for more intelligence
     with which to manage and meter the flow of that data to
     sustain economic growth. Conventional processing
     architectures and hardwired point solutions are not suited
     to these conflicting demands; there is an emerging need for
     a new approach for this data flow processing problem. This
     paper presents ClearSpeed's integrated Network Processor
     design platform that embodies many different levels of
     parallel processing. Designed to balance the bandwidth needs
     with programmability we introduce the MTAP architecture. An
     area and power efficient, fine-grained, scalable,
     multi-threaded parallel processor, designed with a
     'bandwidth-centric' architecture and programmed in C. Based
     on the ClearConnect™ bus, an SoC communication
     architecture with VCI compliant interfaces, a high-bandwidth
     system architecture including a number of hardware
     accelerator units is also described. An example 40Gbit/s
     programmable and scalable classifier/forwarder is presented,
     embodying the concepts of the platform. To complete the
     picture, a comprehensive suite of software and hardware
     development tools is described."
}
@InProceedings{PascoeLoader01,
  title = "{W}orking {T}owards the {A}greement {P}roblem {P}rotocol {V}erification {E}nvironment",