Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
An Optimised Parallel Compiler for Executing Declarative Programs on Transputer Array
By Wang Dingxing, Tian Xinmin, Zheng Weimin, Shen Meiming, Wen Dongchan
Many Declarative Programming Languages (DPLs) such as KL1, Prolog, PARLOG, Miranda and SML are considered attractive candidates for artificial intelligent application and execution on parallel architecture. However, there are many issues such as compile-time granularity analysis, partial evalution, task scheduling and load balancing for the efficient implementations of DPLs on multiprocessor system. In this paper, we take the emphasis on the compiling implementation of PARLOG and SML on a distributed memory multiprocessor system (transputer array). Under the graph rewriting framework, a Heterogeneous Parallel Graph Rewritng Execution Model (HPGREM) and corresponding description Language CIL are proposed. Based on the HPGREM, a parallel abstract machine PAM /TGR (Parallel Abstract Machine for Term Graph Rewriting) and corresponding compilation rules to generate PAM/TGR code are presented. Futhcrmore, an optimised parallel compiler for executing declarative programs on transputer array is described. The performance statistic on a 16-nodes transputer array demonstrates the effectiveness of our model, compiling techniques and compiler.
Complete record...
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