Newsgroups: comp.sys.transputer
From: asskleong@ntuvax.ntu.ac.sg
Subject: Re: Request for information on DMA controllers
Organization: Nanyang Technological University - Singapore
Date: 14 Nov 94 14:08:31 +0800
Message-ID: <1994Nov14.140831.1@ntuvax.ntu.ac.sg>

In article <784369380snz@walker.demon.co.uk>, paul@walker.demon.co.uk (Paul Walker) writes:
> 
> It could be easier to build your own with PLDs?
> 
	Just something came into mind, instead of PLDs how about FPGA chips
such as XILINK (sp ?) ?

> The problem with most of the existing DMA controllers is that they are single
> channel, or at least very few channels, and it sounds as if you may have 
> many channels?
> 
	In our case, a single-channel DMA controllers will be good enough.


> Could you say a little bit more about the application, how many banks of RAM,
> whether you want separate DMA to the different banks, what data rate you 
> actually need and how many channels you need?
> 
	We intend to use the DMA controllers to transfer data from the
external DRAM of the transputer to a pool of memory which can be shared
by other processing elements such as transputers, 80486s, and the like.
We think one-channel DMA controller should be sufficient.

	At the moment we are planning for two banks (each 1MB) for the
external DRAM for each transputer and four banks (each 512 KB) for the
pool of memory.

	The transfer rate, ideally should be approximately 10.5 MB per
second.


> With answers to these questions, it would be easier to help you.
> 
	Thank you very much in advance for your help and advice.


> Paul Walker                             "Making Connections"
> +44 1275 844 864              paul@walker.demon.co.uk
> 

Sincerely,
Soon-Khing Leong



