Newsgroups: comp.sys.transputer
From: djb1@ukc.ac.uk (Dave Beckett)
Subject: Re: C101 hadware info
Organization: University of Kent at Canterbury
Date: Fri, 01 Jul 94 13:02:20 GMT
Message-ID: <114@nutmeg.ukc.ac.uk>


>>>>> About "Re: C101 hadware info", John said:
In article <1994Jul1.023028.20862@lugb.latrobe.edu.au> jtc@ee.latrobe.edu.au (John Catsoulis) writes:
John> In article 2E127DCB@server.uct.ac.za, avl@server.uct.ac.za (Tony van
John> lennep) writes:
Tony> Does anyone have any hardware/interface info on the C101 DS-Link
Tony> interface. The last data-book (T9000 Hardware) that I have, has one page
Tony> dedicated to this device.
Tony> 
Tony> thanks Tony van lennep

John> I have datasheets for the C101 and C104 devices in postscript.  I
John> ftped these from INMOS (I think) late last year, but I can't seem to
John> locate them there anymore. Anyway, I have made these available via
John> anon ftp from our server. You can collect them by anon ftping to

John> ee.latrobe.edu.au

John> and they are in the directory pub/datasheets.

They are originally from ftp.inmos.co.uk in /inmos/projects/ieee/hic/data
and yesterday a new version came out.

You can get them from there or from the Parallel archive at HENSA/Unix
(unix.hensa.ac.uk) but they are VERY LARGE:

/parallel/vendors/inmos/ieee-hic/data/C101-02.ps.Z
	ST C101 Parallel DS-Link Adaptor Datasheet - Preliminary Datasheet.
	This allows high speed serial DS-Links to be interfaced to buses
	peripherals and microprocessors.  It is particular suitable to
	interfacing such devices to interconnects which deal in packets
	consisting of data and header information.  This header information
	may be used to demultiplex packets from different sources and/or
	route them through one or more switches.  It has two modes of
	operations - in the first (Transparent Mode), with packetization
	disabled, it provides simple access to the DS-Link, all data
	provided to the ST C101 is transmitted down the DS-Link.  In the
	second (Packetizing Mode) it can be used by devices such as
	processors to use such things as the ST C104 Packet
	Switch [C104-04.ps.Z below].  In both modes it can be used as one
	of: 16 bit processor i/f, 32 bit processor i/f or 16 bit processor
	i/f with token interfaces. This document includes changes for Revs
	A and B silicon.
	64 pages. 17 Mbytes (17667198 bytes) uncompressed.

/parallel/vendors/inmos/ieee-hic/data/C104-04.ps.Z
	ST C104 Asynchronous Packet Switch - Preliminary Datasheet.
	This is a complete, low latency, packet routing switch on a single
	chip.  It connects 32 high bandwidth serial communications links to
	each other via a 32 by 32 way non-blocking crossbar switch,
	enabling packets to be routed from any of its links to any other
	link.  The links operate concurrently and the transfer of a packet
	between one pair of links does not affect the data rate or latency
	for another packet passing between a second pair of links.  Up to
	100 Mbits/s on each link or 19 Mbytes/s on a singe link. Packet
	rate processing up to 200 Mpackets/s.  Data is transmitted in
	packets with headers and uses that to wormhole via interval
	labelling routing and Universal Routing to eleminate hotspots.
	Includes errata from previous datasheet and changes for Rev B.
	64 pages. 18 Mbytes (18281198 bytes) uncomrpessed.

They are also available via www/gopher and email...

Dave

