Newsgroups: comp.sys.transputer
From: R.Peel@ee.surrey.ac.uk (Roger Peel)
Subject: Re: Memory-Mapped Interfaces; PORTs vs PLACEd variables
Organization: University of Surrey, Guildford, England
Date: Tue, 21 Jun 94 08:30:49 GMT
Message-ID: <1994Jun21.083049.4552@ee.surrey.ac.uk>

In article <PHIL.94Jun20172212@tweety.mrad.com.au>, phil@tweety.mrad.com.au (Phil Nitschke) writes:
|> 
|> I am seeking people's opinions on the following two methods of
|> addressing memory-mapped hardware:
|> 
|>   (a)     Using normal variables which are PLACE'd at the desired
|>           location and written-to/read-from by variable
|>           assignment;
|> 
|>   (b)     Using PORTs which are PLACE'd at the desired location
|>           and addressed as primitive channels.
|> 
|> I want to know if there are any performance (or other) advantages that
|> could be obtained by using one method in preference to the other?

Apart from the benefits of parallel usage checking which have been
mentioned by Andy Rabagliati, consider how an optimising compiler might
consider ports vs.  placed variables.

A port I/O instruction is explicitly programmed and should always be
executed.  A series of memory writes, with no memory read operation
following, could be optimised away with no logical effect on the
program - only the memory-mapped side-effects would be eliminated!
Obviously, a transputer compiler could avoid the problem by not
optimising memory accesses or by just not optimising accesses to placed
variables, but I prefer the freedom of a separate port mechanism.

Another benefit of ports is that an I/O device interfaced by a port may
easily be hived off to a separate processor (or hung on the end of a
Link using a C011) with virtually no code change - simply re-declare
the port to be a channel and do the I/O in another parallel process.

On the negative side, some array operations are rather less flexible
using ports.


Roger M.A. Peel
Department of Electronic and     Phone : +44 483 259284   (0483 from UK)
      Electrical Engineering       Fax : +44 483 34139
University of Surrey             Telex : 859331
Guildford                        Email : R.Peel@ee.surrey.ac.uk
Surrey  GU2 5XH 
United Kingdom

*  

