Newsgroups: comp.sys.transputer
From: martin@inf.rl.ac.uk (Martin Prime)
Subject: 1994 WORLD TRANSPUTER CONGRESS (WTC '94) - Tutorial Program
Organization: Rutherford Appleton Laboratory, Informatics Department, U.K.
Date: 27 May 94 14:40:17 GMT
Message-ID: <14788@cupid.rl.ac.uk>

1994 WORLD TRANSPUTER CONGRESS (WTC '94) - Tutorial Program
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SATURDAY 3 SEPTEMBER
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Embedded Control System Design using Transputers 		Code: SA1
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Presenters  	Andy Bakkers (University of Twente, The Netherlands)
		Peter Croll (University of Sheffield, UK)

Intended audience

Engineering managers, engineers and programmers who have no prior exposure
to parallel programming, and those looking for an improved, dependable 
parallel design methodology.

Objectives

To present an overview of the techniques used to design embedded control
systems using transputers, resulting in a fault tolerant and well
documented system, designed in minimum time.

Overview

*	Introduction
	Showing how present day techniques do not naturally lead to a working
	design. However existing computer aided software engineering tools
	result in a parallel description of a system. Parallel programming
	is the natural way to complete this design cycle.
*	Design methods
	Different design methods will be discussed. The required design method
	should enable rapid prototyping, reusability and intertwining of
	specification and design. Explanation of the Twente approach to
	embedded controller design.  Explanation of the use of the popular
	commercial CASE tool StP (Software Through Pictures) and the
	Hierarchical Coloured Petri Net CASE tool (Design CPN) by Sheffield.
*	Design examples
	Examples of real-time design projects using the techniques described, 
	and showing that the objectives were fully met.


Parallel C Programming for Transputers 				Code: SA2
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Presenters		Peter Clayton (Rhodes University, USA)
			Dyke Stiles (Utah State University, USA)

Intended Audience

Existing or future C programmers who want to get an insight into programming
transputer based parallel systems.

Overview

Transputer hardware fundamentals and major considerations will be addressed.
Topics to be covered:

*	PACT C compiler
	*	Single processor facilities - Task management; Inter-task
		communication
	*	Multiple processor facilities - Communication
	*	Configuration files
	*	Performance figures

*	Logical Systems C, Inmos C, 3L C
	*	Single processor facilities; Multiple processor facilities
	*	Configuration files; Performance figures

*	Basic message passing
	*	Adjacent nodes; Remote nodes; Routers; Multiplexors

*	Single node concurrency
	*	Par; Spawn; Fork-Join
	*	Communication between concurrent processes - Messages
	*	Shared variables - Semaphores; Problems
	*	Examples - Router; Multiplexor; Dining philosophers

*	Multiple node programs
	*	Basic communication; Routing
	*	Examples - Nearest-neighbour communication; Multi-hop
		messages; FFT

*	Advanced systems
	*	Message passing alternatives - Addressing modes; Auto
		routing; Topology independence
	*	Other features - Process management (Local & Remote)
	*	Performance monitoring; Debugging
	*	Example systems - Trollius/Genesys; Tiny; Chimp; Linda;
		EXPRESS; Helios; PAR.C; CSTools
	*	Case studies - relaxation

Attendees will receive at the tutorial a full set of slides and a disk
containing source files of all example programs.



A Multimedia Tutorial on the INMOS Communications Chips		Code: SA3
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Presenters	Peter Thompson (INMOS, Bristol, UK)
		Giovanni Fulantelli (Istituto di Tecnologie Didattiche e
		Formative, Palermo, Italy)

This tutorial will use an original form of technical documentation, named
Active or Multimedia Documentation, as a powerful presentation system to
explore the operation and use of the INMOS Communications Chips, the C104,
C101 and C100.

Intended Audience

Hardware and software engineers interested in a new and powerful form of
systems interconnect, builders of multi-T9000 systems, and anyone interested
in multimedia presentations.

Objectives

To provide, through the Active Documentation, a clear understanding of the
novel interconnect architecture made possible by the new chips.

Overview

The active documentation will be used in a detailed description of the INMOS
Communications Chips, including:

*	DS-Links; link performance
*	C104 Asynchronous Packet Switch
		*Wormhole routing
		*Interval labelling
		*Grouped Adaptive Routing
		*Two-phase routing
*	C101 Parallel Link Adapter
		*Operation
		*Interface Modes
*	C100 System Protocol Converter
		*Conversion Modes
		*System Control Conversion


	
IEEE P1355 Heterogeneous Interconnect				Code: SA4
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Presenter	Colin Whitby-Strevens (INMOS, Bristol, UK)

Intended Audience

Anyone interested in chip to chip, board to board, rack to rack or
intra-office interconnect who wishes to exploit highly integrated circuitry
manufactured in commodity CMOS (or Bi-CMOS for highest speeds) technology.

Objectives

To describe the low cost, low latency, scaleable serial interconnect for
parallel system construction.. The presenter chairs the IEEE Working Group
which is defining the proposed standard which proposes serial interconnect
at speeds of up to 200 Mbit/sec and 1 Gbit/sec  (with possible extension to
3 Gbit/sec) in copper and optic technologies. The activity is about to
extend to ISO/IEC.

Overview

*	Introduction and P1355 technologies summary
*	P1355 Protocol stack
*	Rationale
*	DS-Links
*	TS-Links 
*	HS-Links
*	Routing using P1355 protocols
*	Applications and demonstrators - macrocells and chips
*	Applications and demonstrators - boards and systems
*	Use of P1355 in other standards - VME, FB+, ATM Platform, SCSI, etc.


Distributed Memory Systems Overview				Code: SA5
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Presenter		Traian Muntean (IMAG, Grenoble, France)

Intended Audience

Anyone interested in understanding the trends in parallel distributed
operating systems. This tutorial will provide an overview to prepare people
for the second tutorial (SU5) by the same Presenter on the second day.

Objective

To summarise the many exciting developments in distributed operating
systems since the late 1970s. In the last ten years the emergence of
computing environments using massively parallel computers based on complex
and powerful processors has raised new issues in the process of designing
appropriate operating systems.

Overview

*	Overview of distributed memory system concepts
*	Examination of various design issues
*	Related trends in parallel and distributed operating systems


SUNDAY 4 SEPTEMBER
------------------


CASE Tools for Parallel Systems Development			Code: SU1
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Presenters	Dr Innes Jelly (Sheffield Hallam University UK)
		Dr Ian Gorton (University of New South Wales, Australia)

Intended Audience

The workshop will be of interest to practitioners, researchers, and
teachers who have experience of developing software tools for parallel
processing systems. It will also be relevant to practising software
engineers who are interested in developing expertise in the field of
general parallel computation, and for those researchers who may become
involved in the area of parallel software development methodologies and
tools. The workshop programme will include short presentations of current
research work, demonstrations of CASE tools as well as topic based
discussions sessions.

Objective

The objective of the workshop is to provide a forum for the exchange of
information on current approaches to the construction and employment of
CASE tools to support the development of parallel software systems. At the
"Software Engineering for Parallel Systems" Workshop held last year at WTC
'93, the subject of CASE environments emerged as an important area of
active research. CASE tools are being developed to support parallel
software development methodologies, to provide automated verification of
software and for performance evaluation. We should like to encourage those
involved in the design and implementation of these systems to share their
experiences in an informal interactive workshop.

Overview

The workshop will aim to cover the following non-exhaustive list of topics:
*	practical experiences of developing CASE tools specifically for
	parallel systems
*	adaptation of existing CASE tools for parallel software development
*	Use of meta-CASE tools
*	Design repositories for CASE tools
*	Interoperability of tools
*	Use of CASE tools in industry

Participants will be encouraged to contribute at all stages. Short
papers/extended abstracts can be submitted in advance, and will be
available to all participants as workshop proceedings. Those
wishing to contribute a paper, please contact Innes Jelly (email:
i.e.jelly@shu.ac.uk) as soon as  possible for details. Papers/abstracts to
be submitted to her before 15 July 1994.

We also welcome demonstrations of CASE tools: if you are interested in
setting up a demonstration, please contact Ian Gorton (email:
iango@cse.unsw.edu.au).


Parallel Design Concepts for the Transputer  			Code: SU2
-------------------------------------------------------------------------

Presenters		Roger Peel (University of Surrey, UK)
			Peter Welch (University of Kent, UK)

Intended Audience

Beginners to parallel computing; those with experience of programming the
transputer who need more insights into the process; managers responsible
for structuring complex parallel computations.


Objectives

To explain how to exploit the unique architecture of the transputer (in
particular) and communicating process architectures in general.

Overview

*	Introduction to the philosophy and techniques of designing using
	concurrent processes
*	Communication topics:
	*	synchronous and asynchronous communications, buffering,
		multiplexing  and demultiplexing
	*	software routing of messages between processes
	*	overcoming communication latency using excess parallelism
*	Deadlock - and how to design it out.
*	Real-time programming - reasoning about response times
*	Virtual Channels and the T9000
	*	using shared resource channels; the effects of the fast ALT
		mechanism
	*	virtual channels and routing issues
	*	upgrading existing programs
*	The effect of occam3 on your design
	*	modules and libraries
	*	channel records, remote call channels and shared channels


Formal Methods for Transputing  				Code: SU3
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Presenter		Michael Goldsmith (Formal Systems (Europe) Ltd, UK)
			Brain Scott (Oxford University Computing Laboratory, UK)

Intended Audience

Engineers, programmers and supervisors with prior exposure to parallel
programming and occam.

Objectives

To present an overview of formal techniques for describing, constructing
and verifying parallel programs, and to give a limited introduction to
using such techniques.

Overview

*	Introduction: Formal methods, their uses and benefits in parallel
	and sequential programming.  Specifications.  Ensuring program
	correctness. Issues in parallel and distributed programming.
	Application to occam and transputer-based systems.
*	Occam and formal methods: The suitability of occam - straightforward
	semantics, and a theoretical basis.  Laws of occam programming.
	Transformation, analysis and verification.
*	Constructing and verifying systems: Local techniques for establishing
	global properties.  Deadlock, livelock and examples of rules for
	avoiding them.  Determinism, non-determinism and refinement.
*	Putting it into practice:  Case studies of the T800 and T9000
	transputers. The Draper Transputer Fault-Tolerant Processor.
*	Tools: the use of appropriate tools.  Analysis and transformation.
	Refinement and Proof : FDR - industrial strength verification.
*	Summary: Key features of successful methods.  Applicability - languages
	and systems.  Sources of further information.


Image Processing on Transputers  				Code: SU4
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Presenter		Hugh Webber (DRA (RSRE), Malvern, UK)

Intended Audience

Anyone interested in learning the basic techniques of transputer based
Image Processing. No prior knowledge of either transputers or Image
Processing is required.

Objectives

To provide an introduction to Image Processing techniques and how these
techniques can be implemented on transputers. 

Overview

The tutorial is presented in four sessions:-

*	An Introduction to Image Processing.
	The basic principles of Image Processing will be presented in this
	session. Topics covered will include image pre-processing, correction
	techniques, enhancement, segmentation, analysis and scene recognition.
*	Parallelism in Image Processing.
	This session will present software approaches to parallel image
	processing. In particular a structured programming approach will be
	presented which enables the software to be largely independent of the
	hardware configuration. The design of algorithms using this abstraction
	will be presented along with the advantages of the technique.
*	Image Capture and Display.
	This session will cover the problems inherent in image capture,
	particularly in 'real time'. How such images can be acquired and
	distributed across a transputer array will be described. Equally the
	problems in displaying final processed images will be discussed. Areas
	covered will include the trade off options in terms of system cost, image
	resolution and processing speeds.
*	The Implications of T9000s.
	In this session the potential advantages of the T9000 and C10X family
	of transputer devices will be described. A potential machine design
	will be described, showing how such a machine can be made to efficiently
	scale, in a cost effective manner, from a few processors up to a large
	machine with several hundred processors. The implications and potential
	advantages of the new hardware and software available with T9000
	devices will be described along with methods for gaining the maximum
	potential from these devices.


Issues Related to Parallel Processing Run-Time Models		Code: SU5
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Presenter	Traian Muntean (IMAG, Grenoble, France)

Intended Audience

Anyone interested in learning about the issues relating to run-time models
for both shared and distributed memory systems.

Objectives

To explain all the issues relating to these run-time models to enable the
audience to  understand the issues faced by the designer and implementer.

Overview

*	Process Scheduling
*	Communication Synchronisation
*	Load Balancing
*	Dynamic Configuration
*	Parallel File Systems

---------------------------------------------------------------------------------

		WORLD TRANSPUTER CONGRESS 1994
		   Villa Erba Conference & Exhibition Centre, 
		      Cernobbio, Lake Como, Italy
		         3-4 September 1994
		            Tutorial Programme Registration Form

Registration Form 				Information
Title_________First Name _______________	Registration Fee:
Surname ________________________________
Department (at work)	 _______________	The early booking deadline is 7 July 1994
						Fees per Tutorial (maximum 2 tutorials)
Company/University address___________ __	By 7 July 1994	After 7 July 1994
______________________________________		#120		#145	
______________________________________				
______________________________________		All payments to be made in
_____________________________________		Pounds Sterling A 90% refund
						will be made for cancellations
						received by 15 August 1994.
e-mail___________________________		
Tel. No_______________				Registrations may be transferred
						to a named individual at any
Fax__________________________________		time without financial penalty.
				
Number of Tutorial(s) attending			Lunches, teas and coffee are
						included in the cost of the 
One ___ 	Two ___				Tutorial(s).
Please insert Code(s)				Badges - please indicate below
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that payment is for WTC94. Please attach a copy of your payment slip to this form.
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