Newsgroups: comp.sys.transputer
From: siamakr@cogsci.ed.ac.uk (Siamak Rezaei)
Subject: Better Late than Never!
Organization: Centre for Cognitive Science, Edinburgh, UK
Date: Fri, 25 Feb 1994 11:01:22 GMT
Message-ID: <CLs1AC.4C2@cogsci.ed.ac.uk>

In article <CLoK0n.JBx@cogsci.ed.ac.uk> Alan Smaill <smaill@ed.dcs> writes:
>
>CS Department Colloquium
>
>Place:  6301, JCMB, King's Buildings, Edinburgh
>Time:  2 pm, Friday 25th February
>
>Catherine Barnaby (Inmos)
>
>Modelling a processor core using a queueing network
>===================================================
>
>The Chameleon Project, at Inmos, is developing a family of 64-bit
>microprocessors.  The architecture has a new instruction set, features
>multiple instruction streams, multiple functional units, and is highly
>modular. I shall give an overview of the Chameleon project, and then
>talk about some modelling work which I have done. This models the
>heart of the processor, and provides a method of investigating the
>impact of certain design decisions very quickly.
>
>Tea and coffee in 2510 from 1.30


MC



