Newsgroups: comp.sys.transputer
From: clund@corwin.mc.com (Craig Lund)
Subject: INMOS works to standardize interconnect
Organization: Mercury Computer Systems, Inc.
Date: 15 Feb 1994 17:15:46 -0500
Message-ID: <2jrhii$iv8@corwin.mc.com>

The following article is from the January, 1994, issue of Parallelogram. As 
an experiment, Parallelogram will post one article from each issue. We want 
to see if the postings attract subscribers.


MPP INTERCONNECTION STANDARDS EMERGE
By Craig Lund

Vendors building embedded, massively parallel processors (MPP's) are moving 
to standardize message-passing, MPP interconnects. So far, the scientific MPP 
vendors have ignored these efforts.

VITA, the VMEbus and FutureBus industry's trade association, is the primary 
focus of the embedded world's standardization work. However, the Institute of 
Electrical and Electronics Engineers' (IEEE's) Bus Architecture Standards 
Committee (BASC) is also involved.

Last year, Mercury Computer Systems started the standardization rush when it 
asked VITA to bless its RACEway InterLink (tm). In response, two of Mercury's 
competitors proposed alternative interconnects at VITA's Salt Lake City 
meeting (January 10-11, 1994).

In addition, INMOS asked VITA members to bless IEEE BASC Project 1355 
(Transputer users will instantly recognize the technology behind Project 
1355).

Each proposal provides a high bandwidth, scalable, hardware environment for 
message passing.

None of the proposals support cache-coherent transfers. Cache-coherency 
remains the exclusive province of yet another standard, IEEE Standard 1596-
1992, the Scalable Coherent Interface (see Parallelogram, September 1992, for 
details). However, all of the proposals can transport SCI packets.

Standards are very important in the embedded world. Data acquisition 
subsystems from one vendor must work with computing elements from a second 
vendor, and output devices from a third vendor. All three subsystems must fit 
into a chassis, possibly from a fourth vendor.

When new technology forces change, VITA members must eventually agree upon a 
single standard. If, initially, members cannot agree, VITA typically 
"standardizes" every practical alternative. VITA then lets the market select 
the "real" standard.

In the competition for market share, Mercury's RACEway is clearly winning. 
About a dozen vendors have already committed themselves to RACEway products. 
Another two dozen are close to a decision. Mercury believes RACEway's 
momentum will be unstoppable by VITA's next meeting in early March.

Mercury's competitors are working to slow RACEway's adoption, mainly by 
proposing "better" alternatives that are undeliverable today.

The remainder of this article describes the contenders: Mercury's RACEway, 
Sky Computers' SKYChannel (tm), National Semiconductor's QuickRing (tm), and 
INMOS's P1355.


RACEway
-------

Mercury Computer Systems' RACEway Interlink incorporates a pipelined, circuit 
switching architecture with virtual channels. Each stage is a non blocking, 
six-way, crossbar switch. Designers can configure RACE fabrics in a variety 
of topologies. Examples include ring, Clos, tree, and mesh.

From the CPU's point-of-view, RACEway interface chips provide a common 
address space that contains the CPU's local memory, other processors' local 
memory, as well as VMEbus and VSB address spaces. Processors can communicate 
using this "shared memory," or they can exchange messages. RACEway supports 
point-to-point messages, broadcast messages, and multicast messages. Mercury 
uses partial, profitable, progressive adaptive routing.

Mercury's RACEway Interlink operates at memory speeds, up to 160 
Mbytes/second per connection. Mercury's RACEway chips impose a maximum 
latency of 125 ns. per stage (assuming the requested path through the RACEway 
is available).

RACEway uses the VMEbus P2 connector. Existing VMEbus installations can add 
RACEway capability by pushing a RACEway Interlink Module onto the rear of a 
standard, VMEbus backplane. The Interlink Module contains the RACEway 
crossbar chips, and, optionally, the RACEway to VSBbus interface chip. 
RACEway is 32 bits wide and clocked at 40 MHz.

RACEway includes priority-based routing to support real-time applications. 
There are four priority levels under software control, and an additional 
priority scheme under hardware control. Higher-priority transfers suspend any 
lower-priority circuits that might otherwise temporarily block a transfer.

Routing through RACEway follows directions in a header that interface chips 
automatically add to the beginning of each transfer. When a shared memory 
transaction occurs, the RACEway interface extracts appropriate directions 
from tables maintained in the RACEway interface at each node. Alternatively, 
software message passing libraries can create routing headers.

When interacting with nodes that experience long read latencies, RACEway 
interface chips will split read transactions into two parts: a request and a 
reply. Splitting reads helps reduce contention within the fabric.

Mercury's RACEway interface chips can transfer data blocks as large as 256 
Mbytes. However, Mercury's chips move large blocks in page-sized (2 Kbytes) 
chunks. The number of chunks in a large transfer depends only upon the number 
of page boundaries involved.

RACE systems require two chips: the six-way crossbar switch (six ports is not 
an architectural limit) and a network interface chip. Mercury promises 
several network interface chips, each with a different combination of 
features. Mercury is currently shipping systems incorporating two RACEway 
interface chip types and RACEway crossbar chips.

Mercury believes two other companies are working on RACEway network interface 
chips. In addition, Mercury has stated that a major semiconductor company is 
negotiating for rights to Mercury's chips.

For the future, Mercury promised VITA members: a PMC (PCI) to RACEway chip, 
better hardware support for data integrity, concurrent maintenance 
enhancements, RACEway to RACEway bridges (using Fibre Channel), and a 622 
Mbit ATM end point.

For more information, contact Barry Isenstein at Mercury Computer Systems 
(barry@mc.com). Mr. Isenstein is a technical marketing manager.


SKYChannel
----------

Sky Computers gave the assembled VITA members a high-level SKYChannel 
presentation, but did not provide details. Sky promised a technical briefing 
after it formally announces SKYChannel in February.

SKYChannel looks on the surface much like RACEway. Both require active 
backplanes (or modules pushed onto the back of a passive VMEbus backplane). 
Both use crossbar chips clocked at 40 MHz.

However, SKYChannel is twice as wide as RACEway. To accomplish this, 
SKYChannel simply uses two crossbar chips where RACEway uses one.

Sky's bandwidth goal poses a problem at the P2 connector. There are not 
enough pins to pass a 64-bit data path. Therefore, Sky plans to use a high 
speed serial link through P2.

Sky has not yet decided which serial technology to use. They are leaning 
towards Autobahn from German VME vendor PEP.

Autobahn is a 400 Mbyte/sec serial bus. Autobahn's sponsor is also looking 
for VITA's blessing. At every VITA meeting for the past six months, PEP 
officials have claimed that Autobahn chips are "almost ready." However, many 
engineers outside PEP do not believe Autobahn will ever work as a serial bus 
at the bandwidths PEP promises. Sky's use of Autobahn for point-to-point 
connections appears less risky.

Sky has not yet outlined its routing scheme, priority scheme, or 
implementation latencies. Sky has said that SKYChannel will have a "16 Tbyte 
address space."

Sky's proposal is clearly a "work in progress."


QuickRing
---------

CSPI (the letters no longer stand for anything) wants VITA to bless National 
Semiconductor's QuickRing technology. QuickRing is a parallel collection of 
high-speed, serial links. The QuickRing concept originated within Apple 
Computer's Advanced Technology Group. National Semiconductor adopted 
QuickRing after Apple lost interest.

QuickRing uses a ring topology where the point-to-point connections within 
the ring operate independently (the loss of any single node will bring the 
entire ring down). A ring can have up to 16 nodes. However, National has 
promised ring-to-ring bridges, permitting topologies reminiscent of Kendall 
Square Research's endless rings of rings.

QuickRing is six bits wide and provides a raw transfer speed of 200 
Mbytes/second, between each pair of nodes, when clocked at 50 MHz. QuickRing 
hardware breaks transfers down into packets, each with a maximum payload of 
80 bytes. QuickRing uses virtual-cut-through routing that is not adaptive.

QuickRing employs a flow control protocol between nodes that adds significant 
latency to transfers. For example, the best case latency in a five node ring 
is 1.3 microseconds. Also, QuickRing cannot prioritize packets.

CSPI wants VITA to standardize the QuickRing connector used on VMEbus "beauty 
panels." CSPI's connector choice differs from the connector National 
recommends (although National has endorsed CSPI's effort). CSPI also wants 
VITA members to establish a standard way of moving QuickRing signals across 
the VMEbus P2 connector.

CSPI noted that QuickRing, unlike RACEway, can run over cables up to three 
meters long. CSPI also pushed QuickRing's data integrity features (RACEway 
uses an optional, software, CRC).

QuickRing chips are available immediately from National. CSPI's QuickRing VME 
products do not yet exist. CSPI has convinced two other VMEbus suppliers to 
back its QuickRing proposal: Ariel, a DSP board supplier, and Ixthos, a data 
acquisition vendor.

For more information on QuickRing, contact Sean Long at National 
Semiconductor (tselsc@tevm2.nsc.com). Mr. Long is the marketing manager 
responsible for QuickRing.


IEEE P1355
----------

If you are curious about the Transputer's future, look to IEEE Project 1355 
for an answer. With help from Bull Serial Link Technology, and money from the 
ESPRIT program, INMOS hopes to increase link speeds to as much as 3 
Gbits/second.

Europeans know IEEE Project 1355 as the Open Microsystems Initiative's 
Heterogeneous Interconnect, or simply HIC. It is ESPRIT project 7252.

HIC is a marriage of INMOS's packet switching technology with Bull Serial 
Link Technology's point-to-point serial links. At a high level, the 
combination is a packet switching architecture with wormhole routing. HIC 
supports an adaptive routing scheme that is progressive, profitable, and 
partial.

However, is it real? INMOS's Colin Whitby-Strevens told the VITA meeting that 
"anything is possible, if a customer requests it." However, he added "at this 
moment, we have no firm plans or commitments for specific, commercial 
products [chips]."

HIC has the best "bandwidth per square centimeter" potential of all VITA's 
alternatives. During his presentation, Whitby-Strevens used INMOS's C104 
dynamic packet router chip as an example. The C104 is a 32-way crossbar in a 
208 pin CQFP package. However, the existing C104 cannot begin to approach the 
link bandwidths promised by the HIC research (and standardization) efforts.

INMOS wants VITA to bless a P2 active backplane approach that is physically 
similar to RACEway and SKYChannel.

For more information, contact Colin Whitby-Strevens at INMOS 
(colinws@isnet.inmos.co.uk). Mr. Whitby-Strevens is the manager of 
collaborative projects at INMOS, and chairman of P1355.


---
This article is copyright, 1994, by Fitzroy Publishing, Limited (London). 
Distributing unmodified copies of the article, in electronic form, is 
permitted.

European Headquarters:
Parallelogram                      Tel +44 (0)71 437 7005
Fitzroy Publishing, Limited        Fax +44 (0)71 434 2225
46 Old Compton Street              paragram@cix.compulink.co.uk
London W1V 5PB

North American Office:
Parallelogram                      Tel +1 603 868 2900
3 Langley Road                     Fax +1 603 868 5300
Durham, NH 03824-3424              clund@localk.com

Japan:
SofTek Systems, Inc.               Tel +81 3 3412 6008
BTS Sangenjaya 3F                  Fax +81 3 3412 7990
1-22-7 Sangenjaya                  charr@twics.co.jp
Setagaya-ku, Tokyo 154

