Newsgroups: comp.parallel
From: eugene@pioneer.arc.nasa.gov (Eugene N. Miya)
Subject: Re: Massively Parallel "Pizza Box" really the ICE box
Organization: NASA Ames Res. Ctr. Mtn Vw CA 94035
Date: 15 Sep 1995 15:03:27 GMT
Message-ID: <43c4jv$5el@usenet.srv.cis.pitt.edu>

In article <439ep4$pv1@usenet.srv.cis.pitt.edu> alberto@moreira.MV.COM
(Alberto C Moreira) writes:
>Snip out Russell's good point

>         It's my impression - I may be wrong - that the SHARC is mostly a
>         SIMD node. Each chip has 4 Megabits of on-chip memory; except for 
>         the steep price, there's no reason why a parallel machine 
>         can't be made out of lots of SHARCS and no additional memory. 

You are wrong.
The reason is called software (or lack of).

>         Every generation quadruples the number of gates/chip;

You need to learn a little about the von Neumann bottleneck.
Ivan Sutherland would be a little irked by the inadequacy of this point.

