Newsgroups: comp.parallel
From: alberto@moreira.MV.COM (Alberto C Moreira)
Subject: Re: Massively Parallel "Pizza Box" really the ICE box
Organization: MV Communications, Inc.
Date: 14 Sep 1995 14:38:28 GMT
Message-ID: <439ep4$pv1@usenet.srv.cis.pitt.edu>

In article <4341th$9pu@usenet.srv.cis.pitt.edu> rcarter@best.com (Russell Carter) writes:

>Chips with this not-to-be-exceeded performance are obviously feasible,
>but getting performance out of them on interesting problems is not.
>It makes no sense to hype the chip without details on the memory
>subsystem that is to be riveted to the thing, as IBM has (re)learned
>with the 604.

         It's my impression - I may be wrong - that the SHARC is mostly a
         SIMD node. Each chip has 4 Megabits of on-chip memory; except for 
         the steep price, there's no reason why a parallel machine 
         can't be made out of lots of SHARCS and no additional memory. 
         The chip also has six processor-to-processor ports; all one 
         needs to make a 3-D SIMD machine is to connect the dots.

         Every generation quadruples the number of gates/chip; it is to be
         expected that the next jump will be to 16Mb, and then to 64Mb per 
         chip, just like we went from 1Mb DRAMs to 4Mb and then to 
         16Mb within  the last few years. With increased miniaturization,
         it will become more and more attractive to have all the memory 
         on-chip.

                                                              _alberto_

