Newsgroups: comp.parallel
From: alberto@moreira.MV.COM (Alberto C Moreira)
Subject: Re: "Pizza box" computers
Organization: MV Communications, Inc.
Date: 14 Sep 1995 14:38:30 GMT
Message-ID: <439ep6$pv2@usenet.srv.cis.pitt.edu>

In article <4341ms$9p5@usenet.srv.cis.pitt.edu> pclare@thorn-emi-crl.co.uk (Peter Clare) writes:

>Someone please correct me if I am wrong, but my understanding of the
>SHARC is that it can do *one* 48 bit transfer per clock cycle - giving
>a data throughput of 240 Mbytes/s (at 40 MHz clock).  Still pretty
>impressive! 

     That is right, this is managed by a DMA controller that supervises 
     transfers between the six processor-to-processor ports and the
     communications channels, as well as operations between external
     and internal memory. The chip can even address other SHARCS
     within its own address space, I believe up to four.

      There's a good paper on the chip: "A Monolithic Processing Subsystem",
      IEEE Transactions on Components, Packaging and Manufacturing
      Technology, Part B, Vol 17, No 3, August 1994, by Joe E. Brewer, 
      L. Gray Miller, Ira H. Gilbert, Joseph F. Melia and Douglas Garde.


                                                    _alberto_

