Newsgroups: comp.parallel
From: pclare@thorn-emi-crl.co.uk (Peter Clare)
Subject: Re: "Pizza box" computers
Organization: Central Research Laboratories Ltd
Date: 12 Sep 1995 13:24:44 GMT
Message-ID: <4341ms$9p5@usenet.srv.cis.pitt.edu>

In article <42hnkl$7h7@usenet.srv.cis.pitt.edu>,
   David D Golombek <daveg@athena.mit.edu> wrote:
>and 40 MHz for now.  Given that the chip transmits both a 48 bit instruction
>packet and two 40 bit data packets each clock cycle, it has a bandwidth of 
640
>MBytes/sec.  Now, that's under optimal conditions with no blocking of course,

Someone please correct me if I am wrong, but my understanding of the
SHARC is that it can do *one* 48 bit transfer per clock cycle - giving
a data throughput of 240 Mbytes/s (at 40 MHz clock).  Still pretty
impressive! 

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