Newsgroups: comp.parallel
From: daveg@athena.mit.edu (David D Golombek)
Subject: Re: "pizza box" machine
Organization: Massachusetts Institute of Technology
Date: 5 Sep 1995 14:42:13 GMT
Message-ID: <42hnk5$7h2@usenet.srv.cis.pitt.edu>

In article <4026po$rgh@nova.umuc.edu>,
4011 Student 18 <cm325a18@nova.umuc.edu> wrote:
>>
>>I believe I know what you are referring to-
>>
>>_Information Week_, 6/5/95, p. 100: "Massive Desktop Power."
>>
>>This article describes the Desktop RealTime Engine rolled out on May 15 by 
>>Integrated Computing Engines of Cambridge, Mass., a MIT spinoff company.
>>
>>It is a "briefcase-sized machine" containing 32 33-MHz or 64 40-MHz Super 
>>Harvard Architecture Computer ("Sharc") chips (Analog Devices ADSP-21060). 
>>The two versions are $50K and $99.5K respectively. The article quotes a cost
>>of $11.60/Mflop. The device communicates at 80 Mbps with an EISA PC front end
>
>This price is ridiculous.  O(1) KFLOPS/$ is the best you can do, I'm sorry
>that your benchmarks lead you astray, perhaps memory bandwidth wasn't 
>considered?  Try $300/Mflop for an excellent goal.  Prove me wrong!

Ok, well I'll give it a shot :-)
After reading about the company in EE Times, I checked out their web site
(http://www.iced.com/) because their claims interested me. I then talked
to Analog Devices' Information Center (617) 461-3392 and got the following
information. According to the info, with the ADSP-21060, ICE may be able to  
meet it's claims.  From what Analog is releasing, the chip is available at 33
and 40 MHz for now.  Given that the chip transmits both a 48 bit instruction
packet and two 40 bit data packets each clock cycle, it has a bandwidth of 640
MBytes/sec.  Now, that's under optimal conditions with no blocking of course,
who knows how it does in Real Conditions (tm).  The 48 bit instruction 
packet can contain up to 3 separate instructions, leading to a peak instruction
rate of 120 MFLOPS.  ICE is probably getting the 7.68 GFLOPS mark by putting
64 of them in an array, and making sure they aren't doing redundant 
calculations nor spending too much time communicating between chips.  As
for price/perfomance, Analog sells the 40 MHz 21060 for $422 in quantities
of 1000, so ICE can reasonably expect to meet the $11.60/MFLOP

Overall, from what I've seen, the computer (or "RealTime Engine" as ICE calls
it) should be quite impressive, if they can get the chips to come anywhere 
close to their peak performance numbers.  They'll be releasing their first 
products rsn, so we'll see then.

BTW, the Electronic Engineering Times article I mentioned above was from
the 5/22/95 issue if you're interested.

David Golombek
MIT EE/CS student

