Newsgroups: comp.parallel
From: edemaine@ug.cs.dal.ca (Erik Demaine)
Subject: Memory latency in SMPs
Organization: Math, Stats & CS, Dalhousie University, Halifax, NS, Canada
Date: Mon, 26 Jun 1995 22:45:49 GMT
Message-ID: <DAsxwE.J3q@cs.dal.ca>

Hi folks,

I'm looking for various techniques used to tackle the memory latency problem
on shared-memory multiprocessors.  Sofware-controlled (compiler-based) is the
kind that I'm interested in.

So far, I've found several papers on the following methods:
	1. Data prefetching
	2. Cache coherence (coherent caches)
	3. Multithreading (multiple contexts)
	4. Relaxed memory consistency models (buffering & pipelining memory
	   references)
	5. Data partitioning
	6. Locality optimizations

#5 may be considered to fall into the class of #6.

If you know of any other methods, and/or have some good papers on any of
the above topics (especially #6), please e-mail me at edemaine@ug.cs.dal.ca

Thanks!
Erik
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edemaine@cs.dal.ca  || 01ERIK@ac.dal.ca       || edemaine@is.dal.ca
URL: http://ug.cs.dal.ca:3400/~edemaine/edemaine.html
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