Newsgroups: comp.parallel
From: kamiya@cse.ucsc.edu (Fumiaki Kamiya)
Subject: Re: Maspar MP-2  Router vs rfetch
Organization: CE/CIS Board, UC Santa Cruz.
Date: Mon, 26 Jun 1995 20:46:23 GMT
Message-ID: <KAMIYA.95Jun26134623@arapaho.cse.ucsc.edu>

In article <3sda3k$d51@news.cs.brandeis.edu> Suresh Kalathur <suresh@cs.brandeis.edu> writes:

       vec  : 0 1 2 3 4 5 6 7 8 9  10 11 12 13 14 15
		ss_rfetch(pos, &vec, &vec, sizeof(int));
       vec  : 1 2 3 5 5 6 7 9 9 10 11 13 13 14 15 1 
	     Ha! Processors  3 7 11 15 have a wrong value

I don't think using the same memory location for both source
and destination is a safe thing to do.  This is because
routing, unlike xnet, is potentially done in several steps.
(And if it is done in several steps, you may be writing into
a memory location before the value is read.)  Routing will
take several steps if there's a conflict in the use of
routing channels.  In the above case, this is inevitable as
four PEs are competing for the same routing channel.
(Remember, there's only one routing channel per 16 (=4x4)
PEs.)

Hope this helps.

--
Fumiaki Kamiya


