Newsgroups: comp.parallel
From: Adrian Moga <moga@paris.usc.edu>
Subject: ISCA'95 Fifth Workshop on Scalable Shared Memory Multiprocessors
Organization: University of Southern California, Los Angeles, CA
Date: 17 Apr 1995 10:01:52 -0700
Message-ID: <3n36uh$js9@usenet.srv.cis.pitt.edu>

                            ISCA'95 WORKSHOPS


                            June 19-20, 1995
                       Santa Margherita Ligure, Italy


           Fifth Workshop on Scalable Shared Memory Multiprocessors

           Organized by Michel Dubois (University of Southern California)
                    and Shreekant Thakkar (Intel)


		                ADVANCE PROGRAM


Monday, June 19

8:00	Late registration
8:15	Welcoming Remarks

8:30	Session 1: Hardware Protocols
        Chair: TBD

	1.1 "An Efficient Implementation of Limited Directory Cache Coherence
	Schemes for Shared Memory Multiprocessors" 
	by  P. Mannava, A. Kumar and Laxmi N. Bhuyan (Texas A&M)

	1.2  "The SPEED Cache Coherence Protocol for an Optical
	Multi-access Interconnect Architecture (OMIA)"
	by Timothy Mark Pinkston and Joon-Ho Ha (USC)

	1.3 "Distance Adaptive Update Protocols" by Josep Torrellas,
	Alain Raynaud, and Zheng Zhang (Illinois)

9:45    Coffee Break
	
10:15	Session 2: Hardware Projects I
        Chair: TBD
	
	2.1 "T-Zero: Hardware Support for Distributed Shared Memory
	on a Cluster of Workstations" by Steven K. Reinhardt, 
	Robert A. Pfile, and David A. Wood (Wisconsin)

	2.2 "Globally Coherent Message Passing in the Stanford FLASH"
	by John Heinlein, Kourosh Gharachorloo, and Anoop Gupta (Stanford and DEC)

	2.3 "Scylla: A Memory Controller with Integrated Protocol Engines for
	Distributed Shared Memory Support" by Andreas Nowatzyk, Gunes Aybay,
	Michael Browne, Bill Radke, and Sanjay Vishin (Sun Microsystems)


11:30	Lunch

1:00	Session 3: Performance I
        Chair: TBD
	
	3.1  "Performance Evaluation of the Cache-Coherent Convex SPP-1000 for Earth
	and Space Science Applications" by Thomas Sterling (USRA), 
	Daniel F. Savarese (Maryland) and Phillip Merkey (USRA)

	3.2 "Performance simulations of a Distributed Database
	Machine based on the Scalable Coherent Interface," by
	Haakon Bryhni, Stein Gjessing (Oslo, Norway) and Antonio Schinco (Olivetti).

	3.3. "Integrated Shared Memory and Message Passing for
	Parallel Sparse Matrix Solution" by Fred Chong and John Kubiatowicz (MIT).

	3.4. "Evaluating the Impact of Advanced Memory Systems on 
	Compiler-Parallelized Codes" by Evan Torrie (Stanford), 
	Chau-Wen Tseng (Stanford), Margaret Martonosi (Princeton), Mary Hall (Caltech)

2:40	Coffee Break

3:10	Session 4: Software vs Hardware Consistency
        Chair: TBD

	4.1 "Games You Can Play With Your Protocol"
	by  David Chaiken (Digital, Systems Research Center)

	4.2 "Towards a Software-Only Directory Protocol ---
	Architectural Issues and Performance Effects"
	by Hakan Grahn and Per Stenstrom (Lund, Sweden)

	4.3 "The Performance Effects of Latency, Occupancy and Bandwidth in
	Cache-Coherent DSM Multiprocessors," by
	Chris Holt, Mark Heinrich, Jaswinder Pal Singh, Edward
	Rothberg and John Hennessy (Stanford, Princeton and SGI)

4:25	Panel Discussion: Designing Scalable SMP's using Commodity Microprocessors
	- NUMA vs COMA implementation and Issues for Commodity OS's
	Moderator: Shreekant Thakkar, Intel. 
        
6:00	Adjourn


Tuesday June 20


8:30	Session 5: Performance II
        Chair: TBD

	5.1 "Limits on the Performance Benefits of Multithreading"
	by Beng-Hong Lim (IBM TJ Watson) and Ricardo Bianchini (University of Rochester)

 	5.2 "The Quest Toward a Zero Overhead Parallel Machine: Myth and Reality"
	by Umakishore Ramachandran (Georgia Tech)

	5.3 "Effectiveness of Hardware-Based and Compiler-Controlled
	Snooping Cache Protocol Extensions" by
	Fredrik Dahlgren, Jonas Skeppstedt, and Per Stenstrom (Lund, Sweden)

9:45	Coffee break

10:15	Session 6: Hardware Projects II
        Chair: TBD
	
	6.1 "Avalanche: A Communication and Memory Architecture
	for Scalable Parallel Computing" by John Carter (Utah)

	6.2 "Calibrating RPM" by Koray Oner, Luiz Barroso, Jaeheon Jeong, Adrian Moga,
	Michel Dubois (USC) and Alain Gefflaut (INRIA--France)
	
	6.3 "User-Level DMA for the SHRIMP Network Interface"
	by Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten,
	and Kai Li (Princeton)

11:30 	Lunch


1:00	Session 7: Software vs Hardware Consistency II
        Chair: TBD
	
	7.1 "Efficient Data Sharing with Conditional Remote Memory Transfers"
	by Susan Flynn Hummel (Polytechnic University and IBM TJ Watson).

	7.2 "CRL: High-Performance All-Software Distributed Shared Memory"
	by Kirk L. Johnson, M. Frans Kaashoek, and Deborah A. Wallach (MIT)

	7.3  "A Compiler Algorithm that Reduces Read Latency
	in Ownership-Based Cache Coherence Protocols" by Jonas Skeppstedt 
	and Per Stenstrom (Lund, Sweden)
	
	7.4 "Improving Release-Consistent Shared Virtual Memory
	using Automatic Update"
	by Liviu Iftode, Cezary Dubnicki, Edward W. Felten, and Kai Li (Princeton)

2:40	Coffee Break

3:10	Session 8: COMAs 
        Chair: TBD 

	8.1 "Implementing Simple COMA on S3-MP" by Ashley Saulsbury
	and Andreas Nowatzyk (Sun Microsystems)

	8.2 "Control of Data Replication for Efficiency in a Highly Available
	Cache Only Memory Architecture," by Anne-Marie Kermarrec and Christine Morin
	(IRISA, France)

 	8.3 "Simple Delayed Release Consistency" by Ashley Saulsbury (SICS, Sweden)

4:25	Panel Discussion. Topic TBD. 

6:00	Adjourn

----------------------------------------------------------------------




                        REGISTRATION FORM
                        ISCA 95 Workshops
        June 19-20, 1995 -- Santa Margherita Ligure, Italy

                Early registration deadline May 22, 1995
		(form must be received by this date)

The workshops are:

Workshop 1: Undergraduate computer architecture education, on June 19, 1995
Workshop 2: Pre-hardware performance analysis techniques, on June 20, 1995
Workshop 3: Has been cancelled
Workshop 4: Scalable shared-memory multiprocessors, on June 19-20, 1995



Please mark your selection in the appropriate boxes:

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                ------------------------------------------

                $75     $100    $100    $125     $75 
Workshop 2       []      []      []      []       []


                $150    $200    $200    $250     $150 
Workshop 4       []      []      []      []       []
                -----------------------------------------


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