Newsgroups: comp.parallel
From: hossam@mocha.newcastle.edu.au (Hossam Elgindy)
Subject: 2nd Workshop on Reconfigurable Architectures
Organization: Department of Computer Science, University of Newcastle, Australia
Date: 14 Apr 1995 20:28:08 GMT
Message-ID: <3n36sb$jro@usenet.srv.cis.pitt.edu>

PLEASE NOTE:

1) PLEASE MAKE RESERVATIONS WITH THE RED LION RESORT AS SOON AS
POSSIBLE TO GUARANTEE THE REDUCED RATE. ALSO PLEASE MAKE AIR TRAVEL 
ARRANGEMENTS SOON TO GET REASONABLE RATE AND GOOD FLIGHTS (DIRECT FLIGHTS,
GOOD TIMES, ..., etc.).

2) PLEASE REGISTER TO THE WORKSHOP SOON. YOU CAN E-MAIL YOUR INTENTION OF 
ATTENDING TO (hossam@cs.newcastle.edu.au) OR FAX A SHORT NOTE TO HOSSAM
ElGindy AT (+61 49 21 6929).  EARLY REGISTRATION FOR THE WORKSHOP (NO FEE 
FOR THE WORKSHOP) WILL HELP US MAKE PROPER ARRANGEMENTS FOR THE NUMBER OF 
PEOPLE THAT WILL PARTICIPATE.

3) THERE IS NO SEPARATE FEE FOR THE WORKSHOP AS IT IS PART OF THE
IPPS'95 CONFERENCE. BUT TO PARTICIPATE IN THE IPPS'95 YOU MUST REGISTER.

4) ELCTRONIC VERSION OF THE PROGRAM AND PROCEEDINGS (IN POSTSCRIPT FORMAT)
IS AVAILABLE. TO RECEIVE A COPY SEND MAIL TO hossam@cs.newcastle.edu.au.

==========================================================================

                2nd Reconfigurable Architectures Workshop

                             25 April 1995
                            Red Lion Resort
                       Sanata Barbara, California


                      to be held in conjunction with 
       The Nineth International Parallel Processing Symposium (IPPS)

===========================================================================
                             ADVANCE PROGRAM
          of the 2nd Workshop on Reconfigurable Architectures
==========================================================================

8:30	Welcome & Report from the Chair
	H. ElGindy

9:00	Random graph algorithms for the mesh with subbuses
	D.M. Van Wieren and Q. Stout

9:30	Mid Morning Break

10:00	General tradeoffs between size and time in reconfigurable meshes
	Y. Ben-Asher, A. Cohen and A. Schuster

10:30	Simulating shared memory in real time:
	  On the computation power of reconfigurable meshes
	A. Czumaj, F.M. auf der Heide and V. Stemann

11:00	O(1) Maze routing algorithms on an RMESH
	F. Ercal and H.C. Lee

11:30   An $L_1$ Voronoi diagram algorithm for a reconfigurable mesh
	H. ElGindy and L. Wetherall

12:00	Lunch Break

1:30	A reconfigurable accelerator for 32-bit arithmetic
	R.W. Hartenstein, R. Kress and H. Reinig

2:00	An improved shift switching based parallel counter scheme
	R. Lin and S. Olariu

2:30	A reconfigurable 1-factor hypercubic embedding 
	  interconnection network for parallel processing
	S.M. Bhandarkar

3:00	Minimal deadlock-free compact routing in wormhole
	  switching based injured meshes
	J. Vounckx, G. Deconinck, R. Cuyvers and R. Lauwereins

3:30	Afternoon Break

4:00	FPGAs as configurable computing element
	B.K. Fawcett

4:30	Addressing the computational requirements of image processing
	  with a custom computing machine: An overview
	P.M. Athanas and A.L. Abbott

5:00	Reconfigurable digital image processing system:
	  A structured system approach
	N. Faroughi

5:30	Dicussion

6:00	Official end of Workshop

