Newsgroups: comp.parallel
From: om@dist.dist.unige.it (Mauro Migliardi.)
Subject: Multi Processor SPARC10 cache architecture
Organization: D.I.S.T. - Universita' di Genova
Date: 11 Apr 1995 15:35:21 GMT
Message-ID: <3mje1c$srn@usenet.srv.cis.pitt.edu>

Hi to everyone, I'd like to know if there is a good paper describing
the cache architecture of multi(2X,4X)processor SPARC10 WSs.

Thanks in advance. Bye.

-- 
Mauro Migliardi
PhD student at the University of Genoa 
Department of Telecommunications and Computer Science (DIST)

