Newsgroups: comp.parallel
From: zahir@senan.eng.sun.com (( ))
Subject: mp support in MIPS/ALPHA/PowerPC/P6
Organization: Sun Microsystems Inc., Mountain View, CA
Date: 22 Mar 1995 17:08:08 GMT

[Also posted to comp.arch]

Hi, I would appreciate comments from system architects familiar 
with the latest round of MIPs, Alpha, PowerPC, and P6 processor
anouncements:

[ Feel free to comment on any or all the questions.
  I would very much appreciate facts over speculations however.
  You may also email me directly at:  zahir@sun.com ]

    for each of the above processors:

	1) Does the processor interface propagate memory
	   barrier and synchronizing instructions to
	   the interconnect? How?

	2) Does the processor interface propagate
	   the processor memory model to the interconnect?
	   How? Does is specify the relative ordering of a
	   transaction with respect to preceding transactions?

	   What processor memory models does it support?
	   What memory model does it support/require for PIO?

	3) Does the processor interface support out of order
	   data transfer w.r.t address transfer. Does it support
	   transaction tags? How many bits?
	   Or does the processor require data transfer order
	   be the same as the transaction request order?

	4) Does the processor interface allow scheduling the
	   address and data paths independently? 

	4) Does the processor interface provide a mechanism
	   for indicating "write completion" ?
	   How ? If there are barriers behind the store, what 
	   indicates to the processor to move the 
	   barrier forward?

	   What native support does it provide for it for a 
	   scalable interconnect where reaching the point of global
	   visibility for a write might be many hops away? 
	   Consider non-cached PIO to a remote device 
	   when answering this question.

	5) Does the interface support semantics like:
	   "oops the data I just gave you is no good, discard it
	    and wait for new data", or "oops your request cannot
	    be satisfied, retry later"? How? Does the processor
	    reorder the to-be-retried transaction? block on it?
	    
	6) What page attributes are supported by these processors?
	   (for instance, hw-coherent/incoherent/noncached/IO/etc).
	   How are these attributed made visible to the 
	   interconnect? Separate transaction types? What
	   ordering semantics (if any) are applied to
	   transactions on different page attributes?

	7) How many outstanding cache transactions from the 
	   processor? Does it support prefetch? Does it allow 
	   prefetch data to be delivered out of order ? 
	   Can the prefetch generate dirty victim writebacks? 

	8) How many outstanding dirty victim writeback
	   transactions if the cache is writeback? Is there any 
	   ordering required between the read and the writeback? 
	   Does the writeback from a prior read-writeback pair 
	   block the read in the next read-writeback pair?

	9) What support does the processor have for block copy?
	   Is it out of band or does it pollute the cache?
	   Are there separate transactions for it? Do they
	   have any ordering semantics on them? If not, how is
	   the end synchronized ? (i.e. similar to 4) above).

	10) How large physical address space? i.e. how many PA bits
	    in the address packet?

	11) What "cache coherence" support does the processor have?
	    Is managing the tags of the coherent cache on chip or
	    off chip? If on chip, is it a snoopy cache? or does
	    it require coherence to be maintained outside and
	    only acts on invalidation/copyback requests?

	    Does the interface support point-to-point
	    interconnection? Can it support both bus 
	    and point-to-point? What kind of arbitration protocol
	    does it support?
	    
	12) Does the processor interface have any "name space" 
	    limits?  What are they and how many bits? (ex: 
	    transaction-ids, processor ids, interrupt target ids, 
	    etc.). When answering this question, keep in mind
	    the largest mp machine you could build
	    with the processor in the "glueless mode" (if any), 
	    and the largest server you could build with the 
	    processor using the processors own native support (i.e.
	    no add on extension of name space on the system boards)

Thanks very much in advance,

Kind Regards,
Zahir.

