Newsgroups: comp.parallel
From: rick@cs.arizona.edu (Rick Schlichting)
Subject: Kahaner Report: Int. Symp on Parallel Arch, Algs, Nets (ISPAN'94)
Organization: University of Arizona CS Department, Tucson AZ
Date: 3 Mar 1995 21:14:43 -0700
Message-ID: <3ja73b$ctf@usenet.srv.cis.pitt.edu>

  [Dr. David Kahaner is a numerical analyst currently heading the Tokyo
   office of the Asian Technology Information Program (ATIP). The
   following is the professional opinion of David Kahaner and in no 
   way has the blessing of the US Government or any agency of it.  All 
   information is dated and of limited life time.  This disclaimer should 
   be noted on ANY attribution.]

  [Copies of previous reports written by Kahaner can be obtained using
   anonymous FTP from host cs.arizona.edu, directory japan/kahaner.reports
   or on the World Wide Web (WWW) at URL

          http://www.cs.arizona.edu/japan/www/kahaner_reports.html

  ]


To: Distribution
From: D.K.Kahaner, ATIP-Tokyo [kahaner@cs.titech.ac.jp]
Re: Int. Symp on Parallel Arch, Algs, Nets (ISPAN'94), 12/94 Kanazawa Japan
03/01/95 [MM/DD/YY]
This is file name "ispan-94.95"

Dr. David K. Kahaner
Asian Technology Information Program (ATIP)
Harks Roppongi Building 1F
6-15-21 Roppongi
Minato-ku, Tokyo 106
 Tel: +81 3 5411-6670; Fax: +81 3 5411-6671

ATIP: A collaboration between
   US National Institute of Standards and Technology (NIST)
   University of New Mexico (UNM)
------------------------------------------------------------------------

ABSTRACT. Summary of the International Symposium on Parallel Architectures,
Algorithms, and Networks (ISPAN'94), held Dec. 14-16, 1994, in Kanazawa,
Japan.


ISPAN'94 was held at Ishikawa High-Tech Conference Center on the campus of
the Japan Advanced Institute of Science and Technology (JAIST) on December
14-16, 1994. JAIST is the first Japanese national graduate school for the
advancement of science and technology. It is located on the mountain hills
in the town of Tatsunokuchi about 10 miles south of downtown Kanazawa city,
on the Japan Sea side of the main island of Honshu. (As one of the few
well-preserved historical Japanese cities, Kanazawa is often regarded as a
hidden gem of Japan.)

Proceedings of ISPAN'94 will be published by IEEE Computer Society Press.

The ISPAN'94 Program Chair was Prof. Susumu Horiguchi [HORI@JAIST.AC.JP],
and queries should be addressed to him.


The following summary report was graciously prepared by

  Prof. Vipul Gupta
  Dept. of Computer Science
  State Univ. of New York
  Binghamton, NY 13902-6000
   Tel: (607) 777-2943; Fax: (607) 777-4822
   Email: VGUPTA@CS.BINGHAMTON.EDU


*************************************************************************
*                                                                       *
*         International Symposium on Parallel Architectures,            *
*                Algorithms, and Networks (ISPAN'94)                    *
*                                                                       *
*************************************************************************

The first International Symposium on Parallel Architectures,
Algorithms and Networks was held in Kanazawa, Japan from Dec
14-16, 1994. The symposium was sponsored by the Japan Advanced
Institute of Science and Technology (JAIST) in cooperation with
the IEEE Computer Society Technical Committees on Computer
Architecture and Parallel Processing, the IEEE Computer Society,
the IPSJ Technical Committee on Algorithms, the IPSJ Technical
Committee on Computer Architecture and the IEICE Technical
Committee on Computer Systems.

A total of 110 submissions came from 20 countries worldwide.
Accepted contributions appear in the proceedings published by
the IEEE Computer Society Press, Los Alamitos, California
(ISBN 0-8186-6507-6, Order Number 6507-02). The proceedings also
include invited presentations by Tom Knight (MIT), Richard C.T.
Lee (Providence University, Taiwan ROC), G.J. Li (ICT, Chinese
Academy of Science, China), Howard J. Siegel (Purdue University),
and H. Tanaka (Tokyo University).

The conference was held on the campus of the Japan Advanced Institute
of Science and Technology (JAIST). JAIST was founded in October 1990
as a national graduate institution to conduct basic research in the
fields of information technology and new materials. JAIST is located
in the hills around the town of Tatsunokuchi in Ishikawa prefecture
(about 10 miles south of downtown Kanazawa city) overlooking Japan Sea.
Ishikawa prefecture and Tatsunokuchi town aim at forming a base of advanced
research and development, called the Ishikawa Research Park, in the area
centered around JAIST. It is expected that many of the Japanese companies
engaged in research in these areas will set up research laboratories in the
Ishikawa Research Park.

Presentations at the conference covered a wide range of technical
topics in the areas of parallel architectures and algorithms. The
following is a summary of the invited talks and a panel discussion
titled 'Massively Parallel Computation Towards the 21st Century'.
A copy of the conference program is also included.

Further details about this symposium can be obtained from the
organizers:

	Masayuki Kimura (Program Chair)
	Graduate School of Information Science
	Japan Advanced Institute of Science and Technology
	Tatsunokuchi, Ishikawa 923-12, Japan

      Susumu Horiguchi (Program Co-Chair)
	Graduate School of Information Science
	Japan Advanced Institute of Science and Technology
	Tatsunokuchi, Ishikawa 923-12, Japan

	D. Frank Hsu (Program Co-Chair)
	Dept. of Computer and Information Science
	Fordham University
	Bronx, New York 10458-5198, USA

***********************************************************************
*                                                                     *
*                    Summary of Invited talks                         *
*                                                                     *
***********************************************************************

         Views of Mixed-Mode Computing and Network Evaluation

In his plenary talk, Prof. H.J. Siegel (Purdue University) discussed the
notion of mixed-mode parallelism, where a machine can switch between the
SIMD and MIMD modes of parallelism at instruction-level granularity with
small overhead. The motivation for mixed-mode parallelism stems from the
observation that certain phases of a parallel application may benefit
from SIMD mode parallelism while others may be best suited for MIMD
mode parallelism.

Both the advantages (e.g. better performance) and disadvantages (e.g.
more hardware) of mixed mode parallelism were discussed as also the
relationship of mixed mode parallelism to heterogeneous computing. The
latter refers to the use of different types of machines such as a SIMD
machine, a vector machine, a systolic array etc. to execute different
parts of the same application. While machines used in a heterogeneous
environment can operate concurrently,  different modes in a mixed mode
machine can not overlap. A number of important open problems still
remain to be solved in a mixed-mode/mixed-machine environment. These
include finding the best match for portions of a task to different
machines/modes; automating problem decomposition, matching and
scheduling; and, developing a general model for heterogeneous computing.

The last part of the talk focused on the difficulty of comparing, in a
meaningful way, the large number of network architectures which have
been proposed for parallel machines. While it may be obvious that the
amount of hardware required is a better metric than actual dollar cost
(since the latter can be easily changed by marketing policy); other issues
are more obscure, e.g. how can one compare hardware in different
technologies (optical links v/s bigger buffers) without converting to
dollars.

===================================================================
         NCIC's Research and Development in Parallel Processing

In his invited talk, Prof. Guo-jie Li (lig@waltz.ncic.ac.cn) provided an
interesting overview of the national hi-tech R&D program launched by the
Chinese government. This program, called "863" (since it was launched in
the third month of 1986), concentrates on seven areas: biotechnology,
space technology, information technology, laser technology, automation
technology, energy technology and advanced materials. The program has
a total budget of 1.2 billion US dollars for a 15 year duration from
1986 to 2005. It is expected that during this period, the program
goals will adapt to changing industry and market demands
the latest technological trends.

Advanced computing systems are viewed as the most important subject in the
area of information technology. Current research on advanced computing
systems is directed towards
 * Parallel and distributed computed technology --- including
   Massively Parallel Processing (MPP) systems, Symmetric multi-processor
   (SMP) systems and Network of Workstations (NOW),
 * Intelligent man-machine interfaces and natural I/O (interaction using
   Chinese languages),
 * Advanced software automation technology,
 * Promoting applications of artificial intelligence, and
 * Fundamental theory

One of the original objectives of the 863 program was to build intelligent
computing systems which led to the establishment of the National Research
Center for Intelligent Computing Systems (NCIC for short) in 1990. The NCIC
currently has about 70 high level researchers and is a major player in R&D
in advanced computing technology in China. The NCIC has already developed
the first commercial SMP system in China called Dawning-1. The system
consists  of 4 to 16 Motorola 88K RISC processors and up to 768 MB of shared
memory. Compared to the commercial offerings from IBM and SUN and others,
the Dawning-1 has a much shorter context switch time (17 micro-sec as opposed
to 210 micro-sec for the Sparc-5, 158 micro-sec for the MIPS R4000 and
98 micro-sec for the DEC 5000/240) which allows it to achieve near linear
speedup even for small problem sizes. The machine has been successfully
deployed for the problem of recognizing Chinese characters (reported error
rate is under 0.1%). NCIC also supports the Dawning International Co. Ltd.
which is expected to be the leading supplier of high performance computers
in China. With Motorola as its strategic partner, NCIC and the Dawning Co.
expect to deliver the Dawning-2 (20 Gflops) and the Dawning-3 (200 Gflops),
based on PowerPC processors, in 1996 and 1998, respectively.

Other achievements of the NCIC include the development of an asynchronous,
wormhole routing chip that can be used to create mesh based MPP systems. The
routing chip has five bi-directional physical data channels with a total
bandwidth of 500 MB/s (each unidirectional channel has a b/w of 50 MB/s).
In the future, NCIC expects to develop multi-processor boards for use
as accelerators for workstations, and a parallel system based on an
optical crossbar.

In 1993, the shipment of high performance computers in China was 1.18 times
that in 1992 and according to available forecasts, 1994 shipments should
double those for 1993. This impressive growth is likely to continue for
the foreseeable future fueled by three major projects initiated by the
Chinese government. These are often referred to as the Three Golden Projects
--- development of the Chinese information highway (Golden Bridge project),
Credit card processing and banking infrastructure (Golden Card project),
and EDI systems (Golden Custom project).

=========================================================================
         Massively Parallel Processing Project as a Priority Area
              of Research for the Ministry of Education

[In the following summary of Prof. Tanaka's talk, I have included some
details from other talks which were presented in a special session devoted
to the JUMP-1 Project -- VG]

Prof. Tanaka's (tanaka@mtl.t.u-tokyo.ac.jp) talk described the organization of
the Massively Parallel Processing (MPP) project and an overview of research
results that have been obtained thus far. This project was initiated in
April 1992 by the Ministry of Education of Japan to develop fundamental
technologies for massively parallel processing. The Japanese government
foresees parallel processing as a key technology in the 21st century.

The MPP project consists of five groups of university researchers. Four of
the groups are engaged in developing parallel applications (seven
researchers), programming languages (ten researchers), hardware (eleven
researchers) and operating systems (eight researchers), respectively. The
fifth group (eighteen researchers) plays a managerial role and is responsible
for planning and integrating the activities of the other four. In addition
to being supported by the government, the project also has a number of
industry sponsors including Sun, Fujitsu, Toshiba and Hitachi.

The application group is developing a number of applications in areas such
as finite element methods, computer graphics and simulation/evaluation of
parallel architectures. The focus of the language group is on developing
languages that allow efficient execution of parallel programs and have the
descriptive power to express the potentially complex structure of MIMD
computations. This group has designed two languages: NCX, which is
derived from C and is designed for data-parallel programs; and V,
which is an experimental language designed for MIMD programs and is
based on the dataflow model.

The hardware group is designing a parallel computer called JUMP-1 (short
for Japan University Multi-Processor) which uses Supersparc II processors
and a topology called the Recursive Diagonal Torus. The architecture contains
256 clusters where each cluster consists of four Supersparc processors, two
custom designed fine-grained processors (MBPs), four secondary caches that
interface between CPU and MBP, two network interface processors (NIPs), a
network router, an I/O network interface and a common bus. The MBP connects
directly to the main memory (the secondary caches lie between the CPUs and
MBP) and complements the CPU for short threads implementing fine-grained
computations. The main memory has a tag on each word, useful for implementing
various memory-based synchronization primitives.

The OS group is designing a micro-kernel based operating system called
Comprehensive Operating System (COS) for parallel machines. The initial
target architecture for this OS is Jump-1. The design of COS is aimed
at supporting multi-user and multi-job operation, flexible user
customization, balancing performance and protection (between different
jobs/users), hardware independence (providing users with a standard
application program interface, e.g. PVM, MPI), and distributed shared memory.
The COS structure contains two parts -- POS (short for Partition OS) and
SOS (short for Service OS). The POS provides the mechanism for protecting
an aggregate of hardware resources (e.g. a collection of several
processing elements, some memory regions, portions of the file space and
a set of peripherals) from illegal access from outside the partition.
Application programs need to use several system services such as command
interpretation, file allocation and access, system calls, etc. and these are
provided by SOS modules.

The first detailed design of Jump-1 is complete and a number of special
chips such as cache-controller, memory based processor and network switch
are at the logic design stage. The COS is being tested on a multi-processor
Sun workstation. NCX for AP1000 is in its third version and several parallel
applications have been run and analyzed on AP1000. A demonstration of the Jump
machine is expected within the next year.

=============================================================================

       Transit: Reliable High Speed Interconnection Technology

In his presentation, Prof. Tom Knight (MIT) discussed issues related to the
development of high bandwidth, low latency and fault tolerant networks.
These issues are being addressed as part of the Transit project at the
MIT Artificial Intelligence Laboratory. The project has chosen high radix,
highly dilated, multibutterfly topologies over low dimension meshes such
as those used in the Intel Paragon and some research prototypes (MIT's
J-machine and Stanford FLASH).

As justification for this choice, Prof. Knight pointed out that the
supposed low performance of multistage interconnection networks is
often derived from examination of the most naive form of these
networks, the radix two butterfly network. In comparison, dilated
multistage networks exhibit much better performance. On certain
communication patterns, the standard butterfly topology exhibits very
poor performance. The dilated multibutterfly (which connects wires
randomly within equivalence classes with a high probability of
producing expander graphs) eliminates such worst case behavior.
In addition, unlike simpler local interconnect schemes (e.g. meshes),
multistage networks maintain a constant communication bandwidth per
processor under scaling and exhibit a higher degree of fault tolerance.

Routers in the Transit network have the freedom to selectively drop messages
which they are unable to handle due to error, overload or failure. This
transfers the responsibility of successful message delivery from the
network to the sender but greatly simplifies the hardware and conceptual
structure of the routers.

Prof. Knight also addressed the important issue of integrating low latency
networks with the processor itself. Extremely high performance single
chip processors designed for workstation or PC applications have emerged
in recent years. Since very high volumes are needed to justify the
development cost, none of these processors have significant custom
hardware to enable high performance network interconnection. This has
resulted in a set of parallel architectures (such as the Intel Paragon)
where the interface is done as a custom off-chip component and a dedicated
processor is used to intercept and deliver messages. In such architectures,
traversing several chip boundaries results in excessive delays. To address
this problem, Prof. Knight proposed the development of a processor core
which contains a traditional processor and a section of FPGA logic which is
dynamically reconfigurable for many potential applications.

***********************************************************************
*                                                                     *
*                   Summary of Panel Discussion                       *
*                                                                     *
***********************************************************************

      Massively Parallel Computation Towards the 21st Century

      Panelists: Prof. H. Tanaka (University of Tokyo, Japan)
		 Prof. H. J. Siegel (Purdue University, USA)
		 Prof. R. C. T. Lee (Providence University, Taiwan ROC)
		 Prof. Tom Knight (MIT, USA)
		 Prof. Guo-jie Li (NCIC, China)

  Prof. Tanaka kicked off the panel discussion with his vision of computing
in the 21st century. He envisioned the co-existence of MIMD (general
purpose) machines, SIMD (special purpose) machines, Workstations/PCs
and parallel processing over a network. Based on current technological
trends, he envisioned MIMD processors based on 1 volt, 0.1 micron
technology with 1GHz clocks and 2Gflop performance. A chip would
contain eight such PEs along with 128 MB memory and systems with 100
Tflop performance would be achievable. SIMD machines may be expected
to contain 64K processing elements per multi-chip module. Such systems
would contain 8M processing elements and their performance would be in
the range of 8 Pops (peta operations per second).
  For workstations, a new development would be the use of a separate
chip devoted completely to interface processing. Microkernel based
operating systems would be more widespread and the high performance
computing market would be driven by multi-media, human interfaces and real
time applications.


  Prof. Siegel focused on the problems that must be solved in order to
increase the use of parallel processing. The highlight of this talk
was the engaging art work that used alligators to depict these problems.
An important unresolved issue is the development of a good (practical) model
for parallel programming. Other issues that need to be addressed include
the development of user friendly programming environments with integrated
support for debugging, performance instrumentation, program monitoring,
visualization; automatic parallelization and mapping; and, software libraries
and other mechanisms for enhancing portability.
  Before the commercial market embraces parallel processing in a big way,
we need to increase the user base in this area and must identify large
problem domains of interest where parallel computation is required. We must
also develop portable languages, programming environments and upgradable,
reconfigurable systems.


Prof. Lee made the observation that parallel processing can bring great
rewards but only for very specialized problem domains. He further emphasized
ease of parallel programming as an important issue. Drawing an analogy
between the hierarchical organization of corporate organizations, he
proposed the use of a master slave approach as an intuitive way to develop
parallel programs. A distinguishing feature of this model is the absence
of communication between slaves --- the master is involved in all
communications.

Prof. Knight commented that a major factor hindering the wide spread use
of parallel processing is the dearth of parallel programmers. He used
protein folding simulation as an example to underscore the existence
many problems that can only be solved through massively parallel processing.
He pointed out that parallel architectures of the future may be completely
different from what we are used to today. One such futuristic architecture,
dubbed amorphous computing, consists of a large numbers of processors (with
integrated communication capabilities) embedded in a conductive material.
The processors would be free to move about in the enclosing material,
somewhat like microorganisms in a drop of water. These systems may be
powered by shining light on them or bombarding them with heat rays.

Prof. Li predicted that MPP, SMPs and NOW would continue to coexist in
the near future. SMPs would generally have lower performance that MPPs
due to poorer size scalability (less than 100 PEs). He emphasized the
need for ASIC chips to support MPPs since cost/performance considerations
favor the adoption of main stream processors that lack MPP-friendly features.
Lowering communication overhead would continue to be a key issue for
architects of parallel machines.

****************************************************************************
*                                                                          *
*                           Conference Program                             *
*                                                                          *
****************************************************************************

December 14, 1994

     8:00 -        Registration
     9:15 -  9:30  Opening Remarks
     9:30 - 10:30  Invited Talk
       * Views of Mixed-Mode Computing and Network Evaluation
         Professor H.J. Siegel (Purdue University, U.S.A)
    10:30 - 10:40  Break
    10:40 - 12:10  Session A1 (Parallel Processing)
       * A Massively Parallel Implementation of Pattern Classifiers
         on SIMD and MIMD Architectures
         K.P. Lam (University of Kent, United Kingdom)
       * Texture Analysis for Image Processing on General-Purpose
         Parallel Machines
         L. Boroczky, P. Cremonesi, N.Seaubottlo (Politecnico di
         Milano, Italy)
       * Parallel Relational Database Algorithms Revisited for Range
         Declustered Data Sets
         E. Schikuta (University of Vienna, Austria)
    10:40 - 12:10  Session B1 (Algorithm)
       * An Algorithm for Maintaining Consistent View of Processes
         in Distributed Systems
         D.V. Hung (The United Nations University, Macau)
       * Bounds on the VLSI Layout Complexity of Homogeneous Product
         Networks
         A. Fernandez, K.Efe (University of SW Louisiana, U.S.A.)
       * Integrated VLSI Layout Compaction and Wire Balancing on a
         Shared Memory Multiprocessor : Evaluation of a Parallel
         Algorithms
         R.P.Chalasani, K.Thulasiraman, M.A.Comeau (Concordia
         University, Canada)
    12:10 - 13:10  Lunch
    13:10 - 15:10  Session A2 (Network)
       * Cube-Connected Modules: A Family of Cubic Networks
         G.H. Chen, H.L. Huang (National Taiwan University,
         Republic of China)
       * Building a Better Butterfly: The Multiplexed Metabutterfly
         F.T. Chong, E.A. Brewer, F.T. Leighton, T.F. Knight,Jr.
         (MIT, U.S.A.)
       * Recursive Circulant:  A New Topology for Multicomputer
         Networks
         J.H. Park, K.Y. Chwa (KAIST, Korea)
       * Performance of 4-Dimensional PANDORA Networks
         R. Holt, A.B. Ruighaver (University of Melbourne,  Australia)
    13:10 - 15:10  Session B2 (Graph Theory)
       * Parallel Maximal Cliques Algorithms for Interval Graphs
         with Applications
         C.S. Wang, R.S. Chang (National Taiwan Institute of
         Technology, Republic of China)
       * Parallel Connectivity Algorithms on Permutation Graphs
         Y.W. Chen, S.J. Horng, T.W. Kao, H.R. Tsai, S.S.Tsai
         (National Taiwan Institute of Technology, Republic of China)
       * Parallel Graph Isomorphism Detection with Identification
         Matrices
         L. Chen (Fundamental Research Laboratory, U.S.A.)
       * Undirected Circulant Graphs
         F.P. Muga II (Ateneo de Manila University, Philippines)
    15:10 - 15:20  Break
    15:20 - 17:20  Session A3 (Architecture)
       * Processing Nested Loop Structure with Data-Flow Dependence
         on a CAM-Based Processor HAPP
         K.M. Lu, K. Tamaru (Kyoto University, Japan)
       * Software Pipelining for Jetpipeline Architecture
         M. Katahira, T. Sasaki, H. Shen, H. Kobayashi, T. Nakamura
         (Tohoku University, Japan)
       * Message-Based Efficient Remote Memory Access on a Highly
         Parallel Computer EM-X
         Y. Kodama, H. Sakane, M. Sato, S. Sakai, Y. Yamaguchi
        (Real World Computing Partnership, Japan)
       * Combining Message Switching with Circuit Switching in the
         Interconnection Cached Multiprocessor Network
         V. Gupta (SUNY), E. Schenfeld (NEC Research Institute Inc., U.S.A.)
    15:20 - 17:20  Session B3 (Algorithm)
       * An O(logN loglogN) Time RMESH Algorithm for the Simple
         Polygon Visibility Problem
         S.R. Kim, K. Park, Y.K.Cho (Seoul National University, Korea)
       * A Shortest Path Algorithm for Banded Matrices by a Mesh
         Connection without Processor Penalty
         A. Mei, Y. Igarashi (Gunma University, Japan)
       * Optimal Parallel Algorithm for Edge-Coloring Partial
         k-Trees with Bounded Degrees
         X. Zhou, T. Nishizeki (Tohoku University, Japan)
       * An Efficient Algorithm for Solving the Token Distribution
         Problem on k-ary d-cube Networks
         C.G. Diderich, M. Gengler, S.Ubeda (Swiss Federal Institute
         of Technology, Lausanne, Switerland)
    18:30 -        Reception

December 15, 1994

     9:00 - 10:00  Invited Talk
       * NCIC's Research and Development in Parallel Processing
         Professor G. Li (NCIC, China)
    10:00 - 10:10  Break
    10:10 - 12:10  Session A4 (Fault Tolerance)
       * Advanced Fault Tolerant Routing in Hypercubes
         Q.P. Gu, S. Peng (The University of Aizu, Japan)
       * Contention Sensitive Fault-Tolerant Routing Algorithms for
         Hypercubes
         R. Srinivasan, V. Chaudhary, S.M. Mahmud  (Wayne State
         University, U.S.A.)
       * Cost-Effective Global Fault-Tolerant Multiprocessor
         C.S. Yang, S.Y. Wu (National Sun Yat-Sen University,
         Republic of China)
       * Adaptive Fault-Tolerant Wormhole Routing Algorithms with
         Low Virtual Channel Requirements
         S. Chalasani, R.V. Boppana (University of
         Wisconsin-Madison, U.S.A.)
    10:40 - 12:10  Session B4 (Routing)
       * Gossiping on Mesh-Bus Computers by Packets
         S. Fujita, M. Yamashita, T. Ae (Hiroshima University, Japan)
       * Optimal Total Exchange in Linear Arrays and Rings
         V.V. Dimakopoulos, N.J. Dimopoulos (University of Victoria,
         Canada)
       * Quicksort and Permutation Rouing on the Hypercube and de
         Bruijn Networks
         D.S.L. Wei (The University of Aizu, Japan)
       * Architectural Issues in Designing Heterogeneous Parallel
         Systems with Passive Star-Coupled Optical Interconnection
         R. Prakash, D.K. Panda (The Ohio State University, U.S.A.)
    12:10 - 13:10  Lunch
    13:10 - 14:10  Invited Talk
       * Massively Parallel Processing Systems Projects as a Priority
         Research Area of Ministry of Education
         Professor H. Tanaka (The University of Tokyo, Japan)
    14:10 - 14:20  Break
    14:20 - 16:30  Session A5 (Panel Session)
       * Announcement of Poster Papers
       * Massively Parallel Computation Towards the 21st Century
         H.J.Siegel(Purdue Univ.), G.Li(NCIC), H.Tanaka(Tokyo Univ.),
         R.Lee(Providence Univ.), T.F.Knight(MIT), S.Horiguchi(JAIST)

    14:20 - 16:00  Session B5 (Memory Architecture)
       * Announcement of Poster Papers
       * An Interprocessor Memory Access Arbitrating Scheme for the
         S-3800 Vector Supercomputer
         T. Sakakibara, K. Kitai, T. Isobe, S. Yazawa, T. Tanaka,
         Y. Tamaki, Y. Inagami (Hitachi Ltd., Japan)
       * Efficient Implementation Techniques for Vector Memory Systems
         T. Chiueh, M. Verma, S. Padubidri (SUNY-Stony Brook, U.S.A.)
    16:30 - 16:40  Break
    16:40 - 18:30  Poster Session
       * List of Poster Papers

December 16, 1994

     9:00 - 10:00  Invited Talk
       * A Parallel Algorithm for the Single Step Searching Problem
         Dr. R.C.T. Lee (Providence University, Republic of China)
    10:00 - 10:10  Break
    10:10 - 12:10  Session A6 (Network)
       * Efficient Algorithms for Conservative Parallel Simulation
         of Interconnection Networks
         Y.M. Teo ,S.C. Tay (National University of Singapore,
         Singapore)
       * Performance Evaluation of High-Speed Self-Token Ring LAN
         K. Tanno, A. Koyama, S. Mirza, T. Takeda, S. Noguchi
         (Yamagata University, Japan)
       * A Performance Evaluation Procedure for a Class of Growable
         ATM Switches
         Z. Tsai, K. Yu, F. Lai (National Taiwan University,
         Republic of China)
       * Message Transfer Algorithms on the Recursive Diagonal Torus
         Y. Yang, H. Amano (Keio University, Japan)
    10:10 - 12:10  Session B6 (Parallelization)
       * Cenju-3 Parallel Computer and its Application to CFD
         K. Muramatsu, S. Doi, T. Washio, T. Nakata (NEC, Japan)
       * Distributed Validation of Massively Parallel Machines
         C. Aktouf, O. Benkahla, C. Robach (LGI-IMAG, France)
       * Compiler-Chosen Operator Granularity in a
         Functionally-Programmed Tagged Token Architecture
         G. Jennings (Lulea Institute of Technology, Sweden)
       * A Logic Semantics for a Class of Nondeterministic Concurrent
         Constraint Logic Programs
         H.F. Leung, B.M. Tong (The Chinese University of Hong Kong,
         Hong Kong)
    12:10 - 13:10  Lunch
    13:10 - 14:10  Invited Talk
       * Simple Source Responsible Protocols for Fault Tolerant
         Interconnection
         Professor Thomas F. Knight, Jr. (MIT, U.S.A.)
    14:10 - 14:20  Break
    14:20 - 15:50  Session A7 (Array)
       * Matrix Multiplication on the MasPar Using Distance
         Insensitive Communication Schemes
         X. Sun, F. Lombardi (Texas A&M University, U.S.A.)
       * Mathematic-Physical Engine:Parallel Processing for Modeling
         and Simulation of Physical Phenomena
         V.K. Jain, A.D. Snider (University of South Florida, U.S.A.)
       * A Systolic Array Implementation of Common Factor Algorithm
         to Compute DFT
         S. He, M. Torkelson (Lund University, Sweden)
    14:20 - 15:50  Session B7 (Load Balancing)
       * A Detailed Analysis of Random Polling Dynamic Load Balancing
         P. Sanders (Universitat Karlsruhe, Germany)
       * Increase Analysis in the Total Execution Time of a Parallel
         Program
         D. Li, H. Takagi, N. Ishii (Nagoya Institute of Technology,
         Japan)
       * A Greedy Task Clustering Heuristic that is Provably Good
         M.A. Palis, J.C. Liou, D.S.L. Wei (New Jersey Institute of
         Technology, U.S.A.)
    15:50 - 16:00  Break
    16:00 - 17:30  Session A8 (Scheduling)
       * Strategy and Simulation of Adaptive RID for Distributed
         Dynamic Load Balancing in Parallel Systems
         C. Lin, S. Li (Tsinghua University, China)
       * A Novel Hypercube with Lower Latency
         A. Ahmed (University of Massachusetts Dartmouth, U.S.A.)
       * Organization of Parallel Virtual Machine
         V. Beletsky, T. Popova, A. Chemeris (Academy of Sciences of
         the Ukraine, the Ukraine)
    16:00 - 17:30  Session B8 (JUMP-1 Project)
       * Overview of the JUMP-1, an MPP Prototype for General-Purpose
         Parallel Computers
         K. Hiraki (The University of Tokyo, Japan)
       * Comprehensive Operating System for Highly Parallel Machine
         N. Saito (Keio University, Japan)
       * Research on Programming Languages for Massively Parallel
         Processing
         M. Amamiya (Kyushu University, Japan)

         ********************************************
         *            Poster Session                *
         ********************************************

Algorithm

* Radix-4 Parallel FFT Algorithms on the MasPar$^{tm}$ with
  an Eight-Neighbor Processor Array,
  Toshihiro Taketa, Kuninobu Tanno, Susumu Horiguchi,
  Yamagata University, Japan

* A Reliable Sorting Algorithm on Hypercube Multicomputers,
  Yuh-Shyan Chen, Jang-Ping Sheu,
  National Central University, Taiwan

* Ranking, Unranking, and Parallel Enumerating of Shortest
  Disjoint Paths on Hypercube,
  B. Y. Wu, C. Y. Tang,
  National Tsing Hua University, Taiwan

* A Parallel Algorithm for the Cardinality Graphic Matroid
  Intersection Problem,
  Ying Xu, Harold N. Gabow,
  Oak Ridge National Labratory, U.S.A

* Parallel Ray Casting Algorithm,
  Chong Man Nang, Katherine Mu Qing, David Flyn, Lee Yong
  Tsui, Seah Hock Soon, Daniel Tan T.H., Peter Mack,
  Nanyang Technological University, Singapore

* Several Distributed Algorithms for Runtime Construction of
  Arbitrary-Length Linear Arrays and Rings in the RCH System,
  Issac Yi-Yuan Lee, Sheng-De Wang,
  National Taiwan University, Taiwan

* Parallel Algorithm for a Domination Problem in Weighted
  Permutation Graphs,
  Haklin Kimm,
  University of Tennessee at Martin, U.S.A.

* A Parallel Algorithm to Solve Block Tridiagonal Linear Systems,
  Takashi Naritomi, Hirotomo Aso,
  Tohoku University, Japan

* A Practical View on Parallelisation of Genetic Algorithm,
  J. M\"{a}ntykoski, J. Vuori, J. Skytt\"{a},
  Helsinki University of Technology, Finland

Architecture

* An Optimal Mapping of a Global Array to Hierarchical
  Memory Systems with Three Levels,
  Xiaojie Li, Ken'ichi Harada,
  Keio University,Japan

* Decrease of the Effect of Harzard Due to the Conditional
  Branch by Use of Micro Instruction,
  Masato Abe, Kouki Okabe, Yoshiaki Nemoto,
  Tohoku University, Japan

* A Note on Spare Assignments for Mesh Arrays -Minimizations
  of Dangerous Processors-,
  Itsuo Takanami, Katsushi Inoue, Takahiro Watanabe,
  Iwate University, Japan

* Optimal Task Allocation to Maximize Reliability of
  Parallel and Distributed Computer Systems,
  Chan-Ik Park, Seong-Hwan Lee,
  POSTECH, Korea

* Robust Checksum Tests in Algorithm-Based Fault Tolerance
  on 2-D Processor Arrays,
  Dah-Yea D.Wei, Gi-Yong Song, Jung H. Kim, T.R.N. Rao,
  University of SW Louisiana, U.S.A.

* A Performance Study of Hierarchical Bus-Based Distributed
  Shared-Memory Multiprocessor Systems,
  Wernhuar Tarng, Mingteh Chen, Tein-Hsiang Lin,
  National Hsin-Chu Thechers College, Taiwan

* High-Speed Double Precision Computation of Nonlinear Funtions,
  V. K. Jain, L. Lin,
  University of South Florida, U.S.A.

* Intelligent Code Migration of Sychronization Operation for
  Performance Enhancement on a Multiprocessor,
  Rong-Yuh Hwang, Feipei Lai,
  National Taiwan University, Taiwan

* Design of a Hardware Router for Recursive Circulant Multicomputers,
  Jong-Min Lee, Ji-Yun Kim, Jai-Hoon Chung, Bo Seob Kwon,
  Hyunsoo Yoon, Seung Ryoul Maeng,KAIST, Korea

* A Note on a Single Machine Generalized Due Dates Scheduling Problems,
  C. S. Wong, Monique Yan,
  San Francisco University, U.S.A

* Modular Fault-Tolerant Design and a Reliability Allocation
  Algorithm for Mission-Critical Multiprocessor Architectures,
  Ratan K. Guha, Debasish (Dev) Roy,
  University of Central Florida, U.S.A

* AP1000+: Architectural Support for Parallelizing Compilers
  and Parallel Programs,
  Kenichi Hayashi, Tunehisa Doi, Takeshi Horie, Yoichi
  Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu,
  Hiroaki Ishihata, Tatsuya Shindo,
  Fujitsu Laboratories Ltd.,Japan

* (M$\pi$)$^2$: A Hierarchical Parallel Processing System
  for a Global Illumination Model,
  Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, Tadao Nakamura,
  Tohoku University, Japan

* VPP Fortran and Parallel Programming on the VPP500 Supercomputer,
  Hidetoshi Iwashita, Shin Okada, Makoto Nakanishi, Tatsuya
  Shindo, Hiroshi Nagakura,
  Fujitsu Laboratories Ltd., Japan

* Integrated Memory Array Processor: IMAP - A 3.84 GIPS SIMD
  Processing LSI -,
  Nobuyuki Yamashita, Yoshihiro Fujita, Tohru Kimura,
  Kazuyuki Nakamura, Shin'ichiro Okazaki,
  NEC Corporation, Japan

* Iterative Improvement on Load Balancing Property of Array
  Reconfiguration,
  Ting-Ting Y.Lin, Li-Cheng Tai,
  University of California at San Diego, U.S.A

Network

* Latency Analysis of Multicast Communication,
  Akihiro Fujii, Yoshiaki Nemoto,
  Tohoku University, Japan

* Highly Parallel Computation Model for Setting
  Rearrangeable Type Interconnection Network,
  Issam A.Hamid, Tohoku University of Art \& Design, Japan

* Relationships between the Networks,
  Masaru Takesue, Hosei Univeristy, Japan

* Fault Tolerant Routing for Arrangement Graphs,
  Peter M.Yamakawa, Hiroyuki Ebara, Hideo Nakano,
  Osaka University, Japan

* Virtual Tree: A Remedy for Hot Spot Contention in the Data
  Diffusion Machine,
  Hitoshi Oi, Akiyoshi Wakatani,University of Bristol, U.K.

* Some Characteristics of Q-Stars,
  Chin-Tsai Lin, Ferng-Ching Lin,National Taiwan University, Taiwan

* Improving Dependability of Network Management Systems,
  Elias Proc\'{o}pio Duarte Jr., Glenn Mansfield, Masatoshi
  Miyazaki, Shoichi Noguchi, Tohoku University, Japan

* Varietal Hypercube - A New Interconnection Network
  Topology for Large Scale Multicomputer,
  Shou-Yi Cheng, Jen-Hui Chuang, National Chiao Tung University, Taiwan

* A Fault-Tolerant Cost-effective Combining Structure for
  Multistage Interconnection Network,
  Jen-Hui Chuang, Chien-Chou Lin, National Chiao Tung University, Taiwan

-----------------------------END OF REPORT--------------------------------

