Newsgroups: comp.parallel
From: "William W. Collier" <mpdiag@delphi.com>
Subject: Re: SGI Cache Coherency
Organization: Delphi
Date: 2 Mar 1995 21:34:00 GMT
Message-ID: <3j5dk8$16q@toads.pgh.pa.us>


 
     Josef Schuele (c0031010@ws.rz.tu-bs.de) asked on Feb 20
about cache coherence on the SGI Power Challenge.
 
     Here are the results of some recent tests of SGI machines.
 
     ARCHTEST is a program which runs on a shared memory
multiprocessor and which seeks to detect a failure by the machine
to obey such rules of architecture as:
 
     program order (PO) - all operations occur in the order
                          defined by the program.
 
     write atomicity (WA) - each write appears to occur
     instantaneously.  This is the highest standard of cache
     coherence achievable.
 
     Prof. David J. Lilja and his graduate student, Farnaz
Mounes-Toussi, at the University of Minnesota ran ARCHTEST within
the last few months on an SGI Onyx and an SGI Power Challenge.
 
     They found the Onyx was sequentially consistent (SC), that
is, it obeyed both PO and WA.
 
     The Power Challenge was SC as long as only fixed point
operands were used in the tests.  When both fixed and floating
point operands were used, then the machine failed to obey either
PO or WA.
 
     Lilja is seeking other machines to test.  If you know of
available machines, please contact him at lilja@ee.umn.edu.
 
     Development of ARCHTEST on multiple platforms (including
Windows NT 3.5 and UnixWare 2.0) was supported by the InfoMall of
the Northeast Parallel Architecture Center at Syracuse University
and by Novell (in the form of a beta license for UnixWare 2.0).
 
     For further information on ARCHTEST and the results of
testing fourteen different machines, either send me a note or
access "http://www.infomall.org"; then click on "InfoMall at
Mid-Hudson" and on "Multiprocessor Diagnostics".
 
     Bill Collier   collier@acm.org
 

