Newsgroups: comp.arch,comp.sys.super,comp.parallel,comp.sys.powerpc
From: 881045m (Richard Muise)
Reply-To: 881045m@dragon.acadiau.ca
Subject: Re: Is IBM planning to discontinue POWER2 development?
Organization: Acadia University
Date: Mon, 9 Jan 1995 12:56:10 GMT
Message-ID: <1995Jan8.184545.5581@relay.acadiau.ca>

zxu@monalisa.usc.edu (Zhiwei Xu) writes:


>Is there any truth in this rumor? If so, it would be a pity. We really like
>POWER2's performance. We were able to achieve 136 sustained, single-precision 
>MFLOPS and 199 double-precision MFLOPS, which is more than 50% of the peak 266
>MFLOPS on one POWER2 processor. 

>This was achieved with a purely high-level, real-application  C code
>(about 500 lines) without using and assembly or special library. We heard that
>using Fortran could help even more. We know other people have been able to
>achieve more than 100 sustained MFLOPS in CFD applications.

>If POWER3 is out, what then?

The IBM POWER development will continue with the PowerPC. Currently the POWER2
achieves a peak FP speed of 266MFLOPS at 71.5Mhz, and SpecInt92 of 134, and a 
SpecFp92 of 260. The POWER2 issues six instructions per clock cycle.

The current fastest (and currently not yet in production) PowerPC chip is the
PowerPC 620. At 133Mhz it can issue four instructions per clock cycle, and
has an estimated SpecInt92 of 225 (about double the POWER2) and a SpecFp92
of 300, slightly higher than the fastest POWER2. The PowerPC is also a full
64-bit PowerPC implementation, which accounts for it's higher estimated
benchmarks over the PowerPC 604, which also issues at four instructions per
clock. The MFLOPS rating for the PowerPC 620 will be lower than the
POWER2, due to the fact that the POWER2 has two FP units, and the 620 only
has one. 

The next generation of the POWER, the POWER3 has been rolled over into the
first dual-chip PowerPC, the PowerPC 630, which is expected to be announced
maybe by mid year 1995. Unfortunately, in responding to this post, I could
not find any information on it. I expect it to be again, a full 64-bit 
PowerPC, with most likely 2 or more FP units. Possibly there could be
two short pipeline FP units, which would handle the adds, subtracts, etc,
and one long pipeline unit that could handle square roots, double pres.
divides,etc. I would guess that only two FP instructions could issue per
clock cycle, one of which could be the long FP instruction. This would 
allow following FP instuctions to issue instead of waiting for the 
second pipeline to clear.

One advantage of the PowerPC 630 over the POWER2 is that the POWER2 is a 
nine chip CPU, and the 630 is a two chip CPU. This smaller area of the 
chip can mean increased speed. I don't see any large problems with releasing
the 630 at twice the clock speed of the current POWER2. The current
POWER2 has 22 million transistors, and the 630, with only two chips, certainly
can't be that large, so it should be more relaible, use less power, cheaper to
produce, and takes less area on the motherboards.

Hope that helps a bit,
richard



-- 
Friends : Don't Let Friends Do DOS !	
	881045m @ dragon.acadiau.ca
	richard@admin.acadiau.ca
moderator of Comp.Parallel.    Comp.Parallel address: rmuise@dragon.acadiau.ca


