Newsgroups: comp.parallel
From: abw@axiom.maths.uq.oz.au (Alan Williams)
Subject: Re: SMP vs. MPP
Keywords: MPP, SMP, PVP
Organization: Maths, University of Queensland
Date: Mon, 2 Jan 1995 19:02:12 GMT
Message-ID: <3e2geq$1o2@dingo.cc.uq.oz.au>

In article <3dsr2e$lat@wagner.convex.com>, "Patrick F. McGehearty" <patrick@convex.convex.com> writes:
|> In article <9412271747.AA24335@hikimi.cray.com>,
|> Roger Glover <glover@tngstar.cray.com> wrote:

[computers with physically distributed, logically shared memory]

|> >[1] Cray T3D (I am sure), IBM SP1/SP2 (I think), and Convex Exemplar (I
|> >    think).
|> >
|> As I noted earlier, the Convex Exemplar does provide logically shared
|> memory across all processors.
|> 
|> My understanding was that the IBM SP1/SP2 did not provide user level cache
|> coherent access on the virtual address space of different processors.  Their
|> heavy promotion of message passing as a programming methodology supports
|> that thought.  Does anyone have direct knowledge to the contrary?
|> 
The SP1/SP2 doesn't have logically shared memory. It is distributed, and 
nodes can only exchange data by message passing.

Alan


