Newsgroups: comp.parallel
From: clj@bbn.com (Chris Jones)
Subject: Re: SMP vs. MPP
Organization: BBN Systems and Technologies Division
Date: Mon, 2 Jan 1995 18:53:02 GMT
Message-ID: <CLJ.94Dec30160114@unicorn.bbn.com>

In article <9412271747.AA24335@hikimi.cray.com> glover@tngstar.cray.com (Roger Glover) writes:

   In article <9412202130.AA18009@idaho.SSD.intel.com>, Timothy G. Mattson
   <tmg@SSD.intel.com> wrote:

   |> There have been some attempts to merge SMP and MPP.  KSR is
   |> the most recnet example.

   I thought KSR's memory was only "logically" shared.  IMHO, physically-
   distributed-logically-shared memory is not very SMP-like at all.  

I'm not sure what you mean by this.  If the following paragraph doesn't address
what you were talking about, could you say what it is about p-d-l-s memory you
don't find "SMP-like"?

My opinion, formed during the nearly 7 years I worked for KSR, is that KSR's
memory system *is* "very SMP-like".  Unlike, say, the Standford DASH, a piece
of memory does not have a fixed "home", causing all remote references to be
more costly than local references.  Rather, the hardware moves the data where
it is being used, handling sharing and coherency issues.  One way to think of
it is that each processor has a two level cache: a split .5 megabyte L1 cache
and a 32 Mbyte L2 cache, and where other systems would have global shared
memory, KSR has nothing.  The (trademarked, I think) name AllCache is meant to
convey this.

   |> They were unable to pull it off,
   |> however, and have consequently gone out of business.

Not quite true.  They have stopped manufacturing their systems and have laid
off most of their staff.  Customers are still being supported, and the last
public word I recall was something along the lines of "continuing to pursue
other business opportunities".

--
Chris Jones    clj@bbn.com


