Newsgroups: comp.parallel
From: tom@jaameri.gsfc.nasa.gov (Tom Head)
Subject: Re: SMP vs. MPP
Keywords: MPP, SMP, PVP
Organization: NASA Goddard Space Flight Center -- Greenbelt, Maryland USA
Date: Mon, 2 Jan 1995 17:04:24 GMT
Message-ID: <3e185i$j4e@post.gsfc.nasa.gov>

In article <3dsr2e$lat@wagner.convex.com>, "Patrick F. McGehearty" <patrick@convex.convex.com> writes:
> My understanding was that the IBM SP1/SP2 did not provide user level cache
> coherent access on the virtual address space of different processors.  Their
> heavy promotion of message passing as a programming methodology supports
> that thought.  Does anyone have direct knowledge to the contrary?
> 
> - Patrick McGehearty
>   patrick@convex.com

  Sounds right to me. How is this for a DISTRIBUTED -> SHARED spectrum of 
memory distribution?

SP*,Delta,Paragon -> Maspar MP* -> CM5 -> T3* -> Exemplar -> C90,TRITON

  I put the Maspar seperate because although each processor has its own 
memory, I though having a front-end control processor merited distinction.
I put the CM5 closer to shared memory because the vector units, which is
where the CM5 gets its best performance, is almost like a shared memory
SIMD within a processing node. I have had no experience with KSR, N-Cube or
CM2 and I can not remember what the Encore and Sequent memory layout was,
although I thought they were pure shared-memory, but they may have used
local caches, I dont really know?


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