Newsgroups: comp.arch,comp.sys.super,comp.theory,comp.parallel.pvm
From: panda@cis.ohio-state.edu (Dhabaleswar Panda)
Subject: Int'l Workshop on Parallel Processing, Advance Program (LaTeX)
Organization: The Ohio State University Dept. of Computer and Info. Science
Date: 19 Aug 1994 17:59:23 -0400
Message-ID: <3339vrINNdku@lion.cis.ohio-state.edu>

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\begin{document}
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\large
\vspace*{-.9in}
\begin{center}

\ \ \\
\ \ \\
\ \ \\
\ \ \\
\ \ \\
\ \ \\

{\huge\bf First International Workshop\\ on 
\vspace*{0.2in}\\ Parallel Processing} \\ 
\vspace*{0.6in}
{\bf The Oberoi, Bangalore, India}\\ 
\vspace*{0.6in}
{\bf December 26-31, 1994} \\
\vspace*{1.0in}
\fbox{{\LARGE\bf \sl ADVANCE \ \ PROGRAMME}}\\
\end{center}
\vspace*{1.0in}
\normalsize
\begin{center}
\vspace*{1.0ex}
With support from \\
Department of Science and Technology, Government of India \\
Center for Development of Advanced Computing (CDAC) \\
Board of Research in Nuclear Sciences, India\\
Digital Equipment (India) Limited\\
Tata Information Systems Limited (TISL)\\
Center for Development of Telematics (C-DOT)\\
National Aerospace Laboratories (NAL)\\
Infosys Technologies Limited\\
Motorola India Electronics Private Limited\\
IEEE Bangalore Chapter\\
\ \ \\
\ \ \\
In co-operation with \\
IEEE Computer Society Technical Committee on Parallel Processing (TCPP) \\
IEEE Computer Society Technical Committee on Computer Architecture (TCCA) \\
\end{center}

\newpage
\thispagestyle{empty}
\begin{center}
\fbox{\hspace*{0.5in}{\large\bf ORGANIZING COMMITTEE}\hspace*{0.5in}}
\end{center}

\noindent{\bf WORKSHOP CO-CHAIRS} 
\vspace*{-2.5ex}
\begin{tabbing}
\=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
\>Viktor K. Prasanna, USC \> Vijay P. Bhatkar, CDAC \\
\>Internet: prasanna@halcyon.usc.edu    \>Vox: 91-212-331 507 
\end{tabbing}

\noindent{\bf PROGRAM CO-CHAIRS} \\
\vspace*{-5.0ex}
\begin{tabbing}
\=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
\>Lalit Patnaik, Indian Institute of Science 
\>Satish Tripathi, Univ. of Maryland\\
\end{tabbing}


\vspace*{-3.0ex}

\noindent{\bf PROGRAM COMMITTEE}

\vspace*{-2.5ex}

\begin{tabbing}
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
Arvind, MIT \> Sridhar Mitta, Wipro Infotech Ltd. \\
P. C. P. Bhatt, IIT, Delhi \> C. R. Muthukrishnan, IIT, Madras\\
S. Biswas, IIT, Bombay     \> David Nassimi, NJIT\\ 
Mary M. Eshaghian, NJIT \> 
M. V. Pitke, TIFR \\
Richard F. Freund, NRaD                      \> 
Sartaj Sahni, Univ. of Florida\\
Anoop Gupta, Stanford Univ.                  \> 
R. K. Sen, IIT, Kharagpur\\
Kai Hwang, USC \> 
Y. Singh, Tata Info. Systems Ltd.\\
Sitharama Iyengar, LSU      \> 
Vaidy Sunderam, Emory Univ.\\
Lawrence Jenkins, IISc. \>
K. S. Yajnik, Center for Mathematical\\
H. K. Kaura, BARC                            \> 
Modeling and Computer Simulation\\
\end{tabbing}

\vspace*{-3.0ex}
\noindent {\bf PROGRAM CO-ORDINATOR} \\
\vspace*{-5.0ex}
\begin{tabbing}
Ajay Gupta, Western Michigan University\\
\end{tabbing}


\vspace*{-3.0ex}
\noindent {\bf PROCEEDINGS CO-CHAIRS} \\

\vspace*{-5.0ex}
\begin{tabbing}
\=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
\> Ramesh Rao, Univ. of California, San Diego 
\> C. P. Ravikumar, IIT, Delhi\\
\end{tabbing}

\vspace*{-3.0ex}
\noindent {\bf FINANCE CO-CHAIRS} \\

\vspace*{-5.0ex}
\begin{tabbing}
\=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
\>Suresh Chalasani, Univ. of Wisconsin\> A. K. P. Nambiar, CDAC\\
\end{tabbing}


\vspace*{-3.0ex}
\noindent {\bf COMMERCIAL EXHIBITS/VENDOR PRESENTATIONS CO-CHAIRS} \\

\vspace*{-5.0ex}
\begin{tabbing}
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\= \kill
G. H. Visweswara                       \> S. Sasi Kumar\\
CAD Group, MC Division                  \> CDAC\\
ITI, Dooravaninagar\> Ramanashree Plaza, 2/1 Brunton Road\\
Bangalore - 560 016, India \> Bangalore - 560 025, India\\
Vox: 91-80-851 1211 Extn. 3628 \> Vox: 91-80-558 4271 \\
Fax: 91-80-851 0971/851 1724 \> Fax: 91-80-558 4893 \\
Internet: vish@itibang.ernet.in \> Internet: sasi@cdacb.ernet.in  \\
\end{tabbing}

\vspace*{-3.0ex}
\noindent{\bf LOCAL ARRANGEMENTS CHAIR}\\ 
\vspace*{-5.0ex}
\begin{tabbing}
Anirban Basu, CDAC, Bangalore \ \ Vox: 91-80-558 4982 \ \ Fax: 91-80-558 4893 \\
\end{tabbing}

\vspace*{-1.0ex}
\noindent{\bf PUBLICITY CO-ORDINATORS} \\
\vspace*{-5.0ex}
\begin{tabbing}
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\=xxxxxxxxxxxxxxxxxxxxxxxx\=\kill
Dhabaleswar K. Panda             \> Anil Rao            \> C. P. Ravikumar \\
The Ohio State University        \> Universitiet Utrecht \> IIT, Delhi \\
\end{tabbing}


%check for consistency - names and affiliations

\twocolumn
\thispagestyle{empty}
\begin{center}
\hspace*{1.5in}\fbox{\hspace*{0.5in}{\large\bf IWPP '94 - OVERVIEW}\hspace*{0.5in}}
\end{center}

\vspace*{0.3in}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{{\bf Monday, December 26}}
\centerline{{\small (page 4)}}}}\\
\vspace*{0.2in}
\begin{tabular}{ll}
08:00 AM - 06:00 PM & Registration\\
09:00 AM - 01:00 PM & Tutorial 1\hspace*{0.64in}\\
02:00 PM - 06:00 PM & Tutorial 2\\
\end{tabular}
\end{center}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{\bf Tuesday, December 27}
\centerline{{\small (pages 5 - 8)}}}}\\
\vspace*{0.2in}
\begin{tabular}{ll}
08:00 AM - 06:00 PM & Registration\\
08:15 AM - 09:00 AM & Opening Remarks\\
                  & Inaugural Address\\
09:00 AM - 10:00 AM & Keynote Address 1 \\
10:00 AM - 10:30 AM & Morning Break \\
10:30 AM - 12:30 PM & Session 1 \\
10:30 AM - 06:00 PM & Commercial Exhibits \\
12:30 PM - 01:30 PM & Lunch Break \\
01:30 PM - 03:30 PM & Session 2 \\
03:30 PM - 04:00 PM & Afternoon Break  \\
04:00 PM - 06:00 PM & Session 3  \\
06:00 PM - 08:00 PM & Dinner Break \\
08:00 PM - 10:00 PM & Session 4  \\
\end{tabular}
\end{center}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{\bf Wednesday, December 28}
\centerline{{\small (pages 9 - 12)}}}}\\
\vspace*{0.2in}
\begin{tabular}{r@{\hspace*{3pt}}l@{\hspace*{3pt}}ll}
08:00 AM &-& 06:00 PM & Registration\\
08:30 AM &-& 09:30 AM & Keynote Address 2 \\
09:30 AM &-& 10:00 AM & Morning Break \\
10:00 AM &-& 12 Noon & Session 5 \\
10:00 AM &-& 06:00 PM & Commercial Exhibits \\
12 Noon  &-& 01:30 PM & Lunch Break \\
01:30 PM &-& 03:30 PM & Session 6 \\
03:30 PM &-& 04:00 PM & Afternoon Break  \\
04:00 PM &-& 06:15 PM & Session 7  \\
06:15 PM &-& 08:00 PM & Dinner Break \\
08:00 PM &-& 10:00 PM & Session 8  
\end{tabular}
\end{center}
{\ \ Information on location is included on page~21.}\\
\newpage
\vspace*{0.63in}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{\bf Thursday, December 29}
\centerline{{\small (pages 13 - 16)}}}}\\
\vspace*{0.2in}
\begin{tabular}{r@{\hspace*{3pt}}l@{\hspace*{3pt}}ll}
08:00 AM &-& 06:00 PM & Registration\\
08:30 AM &-& 09:30 AM & Keynote Address 3 \\
09:30 AM &-& 10:00 AM & Morning Break \\
10:00 AM &-& 12 Noon & Session 9 \\
10:00 AM &-& 06:00 PM & Commercial Exhibits \\
12 Noon &-& 01:30 PM & Lunch Break \\
01:30 PM &-& 03:30 PM & Session 10 \\
03:30 PM &-& 04:00 PM & Afternoon Break  \\
04:00 PM &-& 06:00 PM & Session 11  \\
06:00 PM &-& 08:00 PM & Dinner Break \\
08:00 PM &-& 10:00 PM & Session 12  
\end{tabular}
\end{center}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{\bf Friday, December 30}
\centerline{{\small (pages 17 - 19)}}}}\\
\vspace*{0.2in}
\begin{tabular}{r@{\hspace*{3pt}}l@{\hspace*{3pt}}ll}
08:00 AM &-& 06:00 PM & Registration\\
08:30 AM &-& 09:30 AM & Keynote Address 4 \\
09:30 AM &-& 10:00 AM & Morning Break \\
10:00 AM &-& 12 Noon & Session 13 \\
10:00 AM &-& 12 Noon & Industrial Track 1 \\
12 Noon &-& 01:30 PM & Lunch Break \\
01:30 PM &-& 03:30 PM & Session 14 \\
01:30 PM &-& 03:30 PM & Industrial Track 2 \\
03:30 PM &-& 04:00 PM & Afternoon Break  \\
04:00 PM &-& 06:00 PM & Session 15  \\
04:00 PM &-& 06:00 PM & Industrial Track 3 \\
\end{tabular}
\end{center}
\begin{center}
\fbox{\parbox[t]{2.0in}{\centerline{\bf Saturday, December 31}
\centerline{{\small (page 20)}}}}\\
\vspace*{0.2in}
\begin{tabular}{r@{\hspace*{3pt}}l@{\hspace*{3pt}}ll}
08:00 AM &-& 12 Noon & Registration\\
09:00 AM &-& 01:00 PM & Tutorial 3\\
02:00 PM &-& 06:00 PM & Tutorial 4\\
06:00 PM & & & Workshop Adjourns\\
\end{tabular}
\end{center}

\vspace*{3ex}
{\hspace*{-0.25in}The registration form is on page~23.}\\


\onecolumn
\begin{center}
\fbox{\hspace*{0.2in}{\large\bf MONDAY, DECEMBER 26}\hspace*{0.2in}}
\end{center}

\begin{center}
\fbox{\hspace*{0.2in}{\bf 9:00 AM - 1:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Tutorial 1}\\
{{\em Data Parallel Programming using High Performance Fortran}}\\
\vspace*{0.1in}
    { Piyush Mehrotra\\
    Institute for Computer Applications in Science and Engineering}
\end{center}

\noindent
{\bf Description:} High Performance Fortran is a set of extensions to
Fortran 90 designed to facilitate data parallel programming
on a wide variety of parallel architectures. These extensions
provide the user with  high  level  mechanisms  to  control   the
distribution  of  data  and  work  across the target architecture
while leaving the low level machine  specific  details  such  as,
data  communication, to the underlying compiler/runtime system.
This tutorial will use a sequence of examples drawn from
scientific applications to highlight important features 
of the language.

\noindent
{\bf Lecturer:} Piyush Mehrotra received his Ph.D.~in Computer Science
from the University of Virginia. He was a staff scientist at
ICASE for two years before joining the faculty of the
Department of Computer Science, Purdue University. He spent four and a half
years at Purdue before returning to ICASE as a Senior Staff Scientist
where he is currently leading the System Software Research effort.
His main research interests are  programming environments,
compilers, and runtime systems for parallel and distributed environments.
Among other activities, he has been a member of the High Performance
Fortran Forum since its inception and has been intimately involved
with the design of the language.


\vspace*{0.2in}
\begin{center}
\fbox{\hspace*{0.2in}{\bf 2:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Tutorial 2}\\
{{\em 
Introduction to Message Passing and Programming with PVM
}}\\
\vspace*{0.1in}
    { D. N. Jayasimha\\
    The Ohio State University}

\end{center}
 
\noindent
{\bf Description:} 
PVM (Parallel Virtual Machine) is a portable message passing library
which runs on a variety of computing platforms from a cluster of
workstations to massively parallel processors.
The first part of the tutorial will be a brief
introduction to parallel architectures and programming.	 The main part
will detail the use of PVM to write parallel programs.	The last part
will discuss guidelines for writing efficient parallel
programs and include a demonstration.  Knowledge of C or FORTRAN and
programming experience is assumed.  The intended audience include scientists
and engineers who wish to parallelize their applications.



\noindent
{\bf Lecturer:} 
D. N. Jayasimha received his Ph.D. in Computer Science from the University
of Illinois at Urbana-Champaign.  He is on the faculty in Computer and
Information Science at the Ohio State University.  He was a Visiting Research
Scientist at the NASA Lewis Research Center during 1993-94 where he worked on
parallelizing applications using PVM and other message passing libraries.
His research interests are in the areas of communication and synchronization
in parallel computation, parallel architectures, and parallel applications.


\newpage
\vspace*{-5ex}
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf TUESDAY, DECEMBER 27}\hspace*{0.2in}}\\
\ \ \\

\vspace{2ex}

\noindent 
\fbox{{\hspace*{0.2in}\bf 8:15 AM - 9:00 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Opening Remarks:} { Viktor Prasanna, Vijay Bhatkar, Lalit Patnaik,
Satish Tripathi. }\\
{\bf Inaugural Address:} { N. Vittal,} Secretary, Department of Electronics,
Government of India.\\

\vspace{5ex}

\fbox{{\hspace*{0.2in}\bf 9:00 AM - 10:00 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Keynote Address 1: } {\em Future of Parallel Programming}, { Arvind, MIT }\\

\vspace{5ex}

\fbox{{\hspace*{0.2in}\bf 10:00 AM - 10:30 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Morning Break}\\
\ \ \\
\ \ \\

\fbox{{\hspace*{0.2in}\bf 10:30 AM - 12:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 1: Architecture I }\\
{\bf Chair: }{ David Kahaner, ONR-Asia.} \\
\end{center}

%December 27

%1030-1230
%Architecture I
%Chair:   

%99 011
\noindent
{\em Issues in Designing Scalable Systems with k-ary n-cube Cluster-c 
Organization}, Dhabaleswar K. Panda and Debashis Basak,
Ohio State University.


%96 011
\vspace{2ex}\noindent
{\em A Performance Model for Virtual Channel Flow Control in Hypercubes},
Younes M. Boura and Chita R. Das, Pennsylvania State University.


%63 011
\vspace{2ex}\noindent
{\em Dynamic Stream Selection on Multiple Instruction Stream Superscalar 
Architectures}, Miquel
Nicolau i Vila and Teodor Jove I Lagunas, Universitat Ramon Llull.


%50 011
\vspace{2ex}\noindent
{\em The Impact of Coarse Grain Parallelism: A Study of Proteus and 
Paragon Supercomputers}, Allen M. Sansano, Hsiao-Ping Tseng and
Arun K. Somani, University of Washington.


%128 031
\vspace{2ex}\noindent
{\em Fault-Tolerant Hierarchical Network of Hypercubes},
M. Kumar, Curtin University of Technology, Australia.



%28 011
\vspace{2ex}\noindent
{\em Computing with Faulty SIMD Hypercubes},
C. S. Raghavendra, Washington State University.

%4968 021
\vspace{2ex}\noindent
{\em A New Family of Low Diameter Network Topologies with Multiple Loops},
Srabani Sen Gupta, Rajib K. Das, Krishnendu Mukhopadhyaya and Bhabani P. Sinha,
Indian Statistical Institute, Calcutta.

%8 011
\vspace{2ex}\noindent
{\em MPP - The Next Generation: Massively Parallel I/O},
Frank J. Rinaldo, Fermi National Accelerator Laboratory.


\begin{center}
\fbox{\hspace*{0.2in}{\bf 10:30 AM - 6:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Commercial Exhibits (TBA)}
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf TUESDAY, DECEMBER 27}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 12:30 PM - 1:30 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Lunch Break}\\
\end{center}

\vspace{3ex}


\begin{center}
\fbox{{\hspace*{0.2in}\bf 1:30 PM - 3:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 2: Algorithms I }\\
{{\bf Chair: }{Heonchul Park, Samsung Electronics Ltd., Korea.}} \\
\end{center}

%130-330
%Algorithms I
%Chair:   

%90 012
\vspace{1ex}\noindent
{\em Performing Dynamic Permutations on a Coarse Grain Parallel 
Machine}, Ravi Shankar and Sanjay Ranka, Syracuse University.

%118 033
%4901 012
\vspace{3ex}\noindent
{\em A Parallel Search  \& Learn Algorithm for Graph Coloring}, 
C. P. Ravikumar and Rajat Aggarwal, Indian Institute of Technology, Delhi.

%117 012
\vspace{3ex}\noindent
{\em Scalable Parallel Formulations for Sparse Matrix Factorization and 
Interior Point Methods}, Anshul Gupta, Vipin Kumar and George Karypis, University of Minnesota.

%4907  012
\vspace{3ex}\noindent
{\em Mutual Exclusion Based Approach for Adaptive Load 
Sharing in Homogeneous Distributed Systems},
P. Subramanyam, C. R. Muthukrishnan and R. Satyanarayanan,
Indian Institute of Technology, Madras.

%112 012
\vspace{3ex}\noindent
{\em A New Shift Switch Model and Large-Size Parallel Counters},
Rong Lin, State University of New York, Geneseo.

%102 012
\vspace{3ex}\noindent
{\em Progressive Generation of Parallel Solutions for Formally Specified 
Problems}, Mathieu Buffo, Erik Urland, Jose Rolim and Didier Buchs,
Centre Universitaire du Informatique-Universite de Geneve.

%13 012
\vspace{3ex}\noindent
{\em Parallel Discrete-Event Simulation: Algorithms and Analysis},
Sajal K. Das and Falguni Sarkar, University of North Texas.


%7 012
\vspace{3ex}\noindent
{\em A Fast Parallel Thinning Algorithm},
Weian Deng, S. Sitharama Iyengar and
Nathan E. Brener, Louisiana State University.


\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 3:30 PM - 4:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Afternoon Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf TUESDAY, DECEMBER 27}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 4:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 3: Software I }\\
{{\bf Chair: }{Shrikant Inamdar, Motorola India Electronics Limited.}} \\
\end{center}

%4-6
%Software I
%Chair:    MR. SRIKANT INAMDAR, MOTOROLA INDIA ELECTRONICS LIMITED, BANGALORE


%131 013
\vspace{3ex}\noindent
{\em Digital's HPF/Fortran 90 Compiler: Meeting the Challenge of Generating
Efficient Code on a Workstation Farm},
Ranga Raj, Digital Equipment (India) Limited.

%97 013
\vspace{3ex}\noindent
{\em Application-Driven Development of an Integrated Tool Environment 
for Distributed Memory Parallel Processors},
C. Clemen, K. M. Decker, A. Endo, J. Fritscher, G. Jost, N. Masuda,
A. Muller, W. Sawyer, E. de Sturler and B. J. N. Wylie,
Swiss Scientific Computing Center CSCS.

%4920 013
\vspace{3ex}\noindent
{\em Compiling Fortran-D for Multiprocessors},
Ananda R., Gautam S. and Sanjeev Aggarwal,
Indian Institute of Technology, Kanpur. 

%76 013
\vspace{3ex}\noindent
{\em STraNPP: Source to Source Translator for Network-Based Parallel 
Processing}, Alfred C. K. Heng, Wentong Cai, Francis B. S. Lee and
K. K. Lee, Nanyang Technological University, Singapore.

%4964 013
\vspace{3ex}\noindent
{\em EC: A Language for Distributed Computing},
Ashok Kumar Naik and Gautam Barua,
Indian Institute of Technology, Kanpur.

%4966 013
\vspace{3ex}\noindent
{\em Interaction Paradigms for Distributed Object-Oriented Programming},
T. S. Mohan, Indian Institute of Science.

%124 013
\vspace{3ex}\noindent
{\em Efficient Implementation of High Performance Fortran via Adaptive 
Scheduling}, L.V. Kale and Ed Kornkven,
University of Illinois, Urbana-Champaign.

%19 013
\vspace{3ex}\noindent
{\em An Overview of the Opus Language and Runtime System},
Piyush Mehrotra and Matthew Haines, NASA Langley Research Center.



\vspace{7ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 6:00 PM - 8:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Dinner Break}\\
\end{center}


\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf TUESDAY, DECEMBER 27}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 8:00 PM - 10:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 4: Applications I }\\
{{\bf Chair: }{Sajal K. Das, University of North Texas.}} \\
\end{center}

%8-10PM
%Applications I
%Chair:   

%4924 014
\vspace{3ex}\noindent
{\em Parallel Implementation of A Robust Algorithm for Tracking Moving Objects},
S. Das, Indian Institute of Technology, Madras and
B. N. Chatterjee, Indian Institute of Technology, Kharagpur.

%4925 014
\vspace{3ex}\noindent
{\em Parallel Implementation of the EM Algorithm for PET Image Reconstruction},
K. Rajan, L. M. Patnaik and J. Ramakrishna,
Indian Institute of Science.


%89 014
\vspace{3ex}\noindent
{\em High Performance Multi-standard Image Compression Coprocessor 
for Multi-media},
Heonchul Park, Samsung Electronics.

%116 014
\vspace{3ex}\noindent
{\em A VLSI Architecture for Approximate Tree Matching},
Raghu Sastry and N. Ranganathan, University of South Florida.

%4938 014
\vspace{3ex}\noindent
{\em Parallel Image Processing Software on ANUPAM},
Rashmi Rastogi, Sudhir Shetiya, Laxmi Phadke and Sunanda Shouche,
Bhabha Atomic Research Centre, Bombay.

%4992 014
\vspace{3ex}\noindent
{\em Interactive Parallel Code Generator for Flosolver Parallel Computer},
C. R. Srinivasan, National Aerospace Laboratories, Bangalore.

%84 014
\vspace{3ex}\noindent
{\em Application of JPEG Algorithm on SHIVA Parallel Architecture},
Savitridevi G. Bevinakoppa, Nalin K. Sharda and
Hema Sharda, Victoria University of Technology.

%126 014
\vspace{3ex}\noindent
{\em Recoverable Data Structures for Supporting Parallel Database Applications},
Krithi Ramamritham and Lory Molesky, University of Massachusetts.



\vspace{7ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 10:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Adjourn for the day}\\
\end{center}

\newpage
\vspace*{-5ex}
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf WEDNESDAY, DECEMBER 28}\hspace*{0.2in}}

\vspace{4ex}

\fbox{{\hspace*{0.2in}\bf 8:30 AM - 9:30 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Keynote Address 2: }{\em SmartNet Scheduling for Heterogeneous Computing}\\ 
{Richard F. Freund, Naval Research and Development Center}\\

\vspace{4ex}

\fbox{{\hspace*{0.2in}\bf 9:30 AM - 10:00 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Morning Break}\\
\ \ \\
\ \ \\

\fbox{{\hspace*{0.2in}\bf 10:00 AM - 12:00 Noon}\hspace*{0.2in}}\\
\  \\
{\bf Session 5: Architecture II }\\
{\bf Chair: }{S. V. Raghavan, Indian Institute of Technology, Madras.} \\
\end{center}

%December 28

%10-12
%Architecture II
%Chair:    PROF. S.V. RAGHAVAN, INDIAN INSTITUTE OF TECHNOLOGY, MADRAS

%111 021
\vspace{1ex}\noindent
{\em Parallel Computations on Heterogeneous Workstation Clusters and 
Distributed-Memory Parallel Computers},
Vikram A. Saletore and J. Jacob, Oregon State University.

%580 021
\vspace{3ex}\noindent
{\em RENNS- an Experimental Computer System with a Reconfigurable 
Interconnection Network},
Jon G. Soldheim and Gaute Myklebust, Norwegian Institute of Technology.

%44 021
\vspace{3ex}\noindent
{\em Comparison of Multiplexing Schemes for Wormhole-Routed 
Distributed Memory Multiprocessors},
Kant C. Patel, Jeff A. May and D. N. Jayasimha,
Ohio State University.


%31 021
\vspace{3ex}\noindent
{\em An Integrated Approach to Distributed Shared Memory},
Alan L. Cox, Sandhya Dwarkadas and Willy Zwaenepoel,
Rice University.

%4 021
\vspace{3ex}\noindent
{\em Twine RISC: A High Performance Multithreaded RISC Architecture},
Rajat Moona, Massachusetts Institute of Technology.


%4982 021
\vspace{3ex}\noindent
{\em Reliability Evaluation of Multistage Interconnection Networks by 
Network Decomposition}, 
C. R. Tripathy, R. N. Mahapatra, R. B. Mishra and S. Patra,
Indian Institute of Technology, Kharagpur.

%30 011
\vspace{3ex}\noindent
{\em Cumulative Performance Measures for Gracefully Degradable 
Multistage Interconnection Networks},
Amiya Bhattacharya, Ramesh Rao and Ting-Ting Y. Lin,
University of California-San Diego.

%109 021
\vspace{3ex}\noindent
{\em An Incessantly Coherent Cache Scheme for Shared Memory 
Multithread Systems},
S. K. Nandy and Ranjani Narayan, Massachusetts Institute of Technology.



\begin{center}
\fbox{\hspace*{0.2in}{\bf 10:00 AM - 6:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Commercial Exhibits (TBA)}
\end{center}




\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf WEDNESDAY, DECEMBER 28}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 12:00 Noon - 1:30 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Lunch Break}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 1:30 PM - 3:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 6: Algorithms II }\\
{{\bf Chair: }{Rong Lin, State University of New York at Geneseo.}} \\
\end{center}

%130 330
%Algorithms II
%Chair:   

%23 022
\vspace{1ex}\noindent
{\em Task Redistribution in Faulty Networks Using Evolutionary 
Strategies}, Garry Greenwood, Ajay Gupta and Mark Terwilliger,
Western Michigan University.


%4977 022
\vspace{3ex}\noindent
{\em Shared Memory Multiprocessor  Implementation of Volume Rendering },
S. Manohar and C. E. Prakash, Indian Institute of Science.

%55 022
\vspace{3ex}\noindent
{\em Superlinear Speedup in Multiprocessing Environment},
Vishwani D. Agrawal, AT\&T Bell Labs.

%4942 022
\vspace{3ex}\noindent
{\em An Efficient Algorithm for the Partitionable Independent Task 
Scheduling Problem using Lookahead - Search},
R. S. Ramesh and C. Shiva Rama Murthy,
Indian Institute of Technology, Madras.

%26 022
\vspace{3ex}\noindent
{\em Algorithms for Efficiently Partitioning a Class of Parallel 
Computations},
Bhagirath Narahari and Rahul Sinha,
George Washington University.


%4915 022
\vspace{3ex}\noindent
{\em On Computing Kirkpatrick Decomposition in Parallel},
Sanjeev Saxena, Indian Institute of Technology, Kanpur.

%4943 022
\vspace{3ex}\noindent
{\em A Parallel Evolutionary Programming Based Channel Router}, 
B. B. Prahlada Rao and R. C. Hansdah,
Indian Institute of Science.

%101 022
\vspace{3ex}\noindent
{\em Analysis and Modeling of Image Processing Algorithms on Parallel 
Computing Systems},
N. Comino and V. Lakshmi Narasimhan, University of Queensland.



\vspace{6ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 3:30 PM - 4:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Afternoon Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf WEDNESDAY, DECEMBER 28}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 4:00 PM - 6:15 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 7: Software II }\\
{{\bf Chair: }{Y. Singh, Tata Information Systems Limited.}} \\
\end{center}

%4-615(Note: there are 9 presentations here)
%Software II
%Chair:    DR. Y. SINGH, TATA INFORMATION SYSTEMS LIMITED, BANGALORE 

%4939 023
\vspace{3ex}\noindent
{\em ANUPAM  Programming Environment},
S. M. Mahajan, P. S. Dhekne, H. K. Kaura, K. Ramesh and K. Rajesh,
Bhabha Atomic Research Centre, Bombay.

%100 023
\vspace{3ex}\noindent
{\em A Loop Distribution Technique for Parallel Machines for Irregular 
Computations},
Mohammed Raziuddin, Ravi Ponnusamy and Alok Choudhary,
Syracuse University.

%93 023
\vspace{3ex}\noindent
{\em A Framework for Multithreaded X Client Development},
Murali V. Srinivasan, SunSoft Inc.

%4953 024 - moved to this session 8/12
\vspace{3ex}\noindent
{\em Performance of ScaLapack on PARAM},
Kamal Kumar Jain, M. Kishore Kumar and Anirban Basu,
Centre for Development of Advanced Computing, Bangalore.

%74 023
\vspace{3ex}\noindent
{\em A Comparative Study of Design Approaches for Parallel Programming 
Languages}, Wolfgang Gellerich and M. M. Gutzmann,
University of Stuttgart.

%4940  023
\vspace{3ex}\noindent
{\em A Model for Parallel Processing Software Development},
Rajib Mall, Indian Institute of Technology, Kharagpur.

%10 023
\vspace{3ex}\noindent
{\em The PARADIGM Compiler for Distributed Memory Message Passing 
MIMD Multicomputer},
P. Banerjee, J. Holm, A. Lain, D. Palermo, S. Ramaswamy
and E. Su, University of Illinois, Urbana-Champaign.

%21 023
\vspace{3ex}\noindent
{\em High Performance Fortran Type Compilers for Irregular and Block 
Structured Problems},
Joel Saltz, Raja Das, Yuan-Shin Hwang, Bongki Moon
and Shamik Sharma, University of Maryland-College Park.

%73 023
\vspace{3ex}\noindent
{\em Distributing Code in A Parallel Fine Grain Machine},
Youssef Latrous and Guy Mazare, LGI/IMAG, France.



\vspace{6ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 6:15 PM - 8:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Dinner Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf WEDNESDAY, DECEMBER 28}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 8:00 PM - 10:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 8: Applications II }\\
{{\bf Chair: }{Bhagirath Narahari, George Washington University.}} \\
\end{center}

%8-10
%Applications II
%Chair:   

%103 023 - moved to this session 8/12
\vspace{1ex}\noindent
{\em Integration of Task and Data Parallelism},
R. Krishnaiyer and B. Avalani,
Syracuse University.

%119 024
\vspace{3ex}\noindent
{\em A Parallel Discrete Event Simulator and its Application to Circuit 
Simulation},
Rajive Bagrodia, University of California at Los Angeles.

%4903  024
\vspace{3ex}\noindent
{\em Stability and Performance of Distributed Simulators for Open Queueing Networks},
Rajeev Shorey and Anurag Kumar, Indian Institute of Science.

%4973 024
\vspace{3ex}\noindent
{\em Application of Timed Token Protocol for Communications in 
an Application Specific Parallel Processing Architecture for 
Real Time Control of an MTDC System},
V.~Shyam and H.~S.~Chandrasekharaiah, Indian Institute of Science.

%4987 023
\vspace{3ex}\noindent
{\em Porting Realistic Applications to HPF - a Case Study},
Sumana S. and U. Nagaraj Shenoy,
Centre for Development of Advanced Computing, Bangalore.

%9 023
\vspace{3ex}\noindent
{\em High Performance Computer for Land Cover Dynamics},
Larry Davis, Rama Chellappa, Joel Saltz, Joseph J\'{a}J\'{a},
Rahul Parulekar and Alan Sussman, University of Maryland-College Park.

%114 023
\vspace{3ex}\noindent
{\em Large Parallel Compact Coding of Satellite Images with Wavelet 
Packet},
Andreas Uhl, University of Slazburg-Austria.

%127 024
\vspace{3ex}\noindent
{\em Distributed Quad-Tree Processing of Vector Data},
S. Venkatesh and D. Kieronska, Curtin University of Technology, Australia.



\vspace{6ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 10:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Adjourn for the day}\\
\end{center}


\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf THURSDAY, DECEMBER 29}\hspace*{0.2in}}

\vspace{3ex}

\fbox{{\hspace*{0.2in}\bf 8:30 AM - 9:30 AM}\hspace*{0.2in}}\\
\ \ \\
\end{center}
\centerline{{\bf Keynote Address 3: }{\em Compiler \& Library Support for Irregular Problems
on High~Performance~Architectures}}

\vspace*{-2.5ex}
\begin{center}
{Joel Saltz, University of Maryland}\\

\vspace{5ex}

\fbox{{\hspace*{0.2in}\bf 9:30 AM - 10:00 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Morning Break}\\
\ \ \\
\ \ \\

\fbox{{\hspace*{0.2in}\bf 10:00 AM - 12:00 Noon}\hspace*{0.2in}}\\
\  \\
{\bf Session 9: Architecture III }\\
{\bf Chair: }{J. Mohan Kumar, Curtin University of Technology, Autstralia.} \\
\end{center}

%December 29
%10-12
%Architecture III
%Chair:    DR. J. MOHAN KUMAR, CURTIN UNIVERSITY OF TECHNOLOGY, AUSTRALIA

%65 031
\noindent
{\em Issues in Understanding the Scalability of Parallel Systems},
Umakishore Ramachandran, H. Venkate-\\
swaran, Anand Sivasubramaniam
and Aman Singla, Georgia Institute of Technology.

%4905 034
\vspace{3ex}\noindent
{\em Parallel Detection of Multiple Faults in Redundant
Path Multistage Interconnection Network},
U. Maulik, Visva Bharathi University, Shantiniketan,
S. Bandyopadhyay, Indian Statistical Institute, Calcutta
and S. Bhattacharya,
Technical Teachers' Training Institute, Calcutta.

%110 031
\vspace{3ex}\noindent
{\em A K-level Binary Tree Embedded in a Symmetrical Reconfigurable 
Network}, Tirumale Ramesh, Saginaw Valley State University.

%85 031
\vspace{3ex}\noindent
{\em A Cost Effective Unidirectional Binary (UB)- Tree Architecture},
Ravi Mittal and Ashok K. Agrawala, University of Maryland-College Park.


%4974 031
\vspace{3ex}\noindent
{\em Design of a High Speed Communication Controller for a Multicomputer 
System - An FSM approach},
M. Srinivasan, B. Nagabhushana and M. Muralidharen,
Indian Institute of Science.

%4961 031
\vspace{3ex}\noindent
{\em Memory Coupled Scalable Multiprocessors},
A. Varshneya, B. Madan and M. Balakrishnan,
Indian Institute of Technology, Delhi.


%4950 031
\vspace{3ex}\noindent
{\em Fault Tolerance in Hypercube Based Parallel Architectures}, 
N. Singhi and S. Sanyal,
Tata Institute of Fundamental Research, Bombay and
I. Shriniwas, Victoria Jubilee Technical Institute, Bombay.


%4921 031
\vspace{3ex}\noindent
{\em Data Communication in the Star Communication Network},
Dilip K. Saikia and Ranjan K. Sen, Indian Institute of Technology, Kharagpur.



\begin{center}
\fbox{\hspace*{0.2in}{\bf 10:00 AM - 6:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Commercial Exhibits (TBA)}
\end{center}




\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf THURSDAY, DECEMBER 29}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 12:00 Noon - 1:30 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Lunch Break}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 1:30 PM - 3:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 10: Software III }\\
{{\bf Chair: }{N. Balakrishnan, Indian Institute of Science.}} \\
\end{center}

%130-330PM
%Software III
%Chair:    PROF. N. BALAKRISHNAN, INDIAN INSTITUTE OF SCIENCE, BANGALORE

%12 032
\vspace{1ex}\noindent
{\em Partitioning Problems in Heterogeneous Distributed Computing},
M. Ashraf Iqbal, Engineering University-Pakistan.

%48 032
\vspace{3ex}\noindent
{\em Transformation Based Development of Efficient Programs for 
Massively Parallel Architectures},
M. M. Gutzmann, University of Jena and
S. Kinderman, University of Erlangen.

%118 032
\vspace{3ex}\noindent
{\em Runtime Support for Task-Parallel Languages},
I. Foster, C. Kesselman and S. Tuecke, California Institute of Technology.


%1 032
\vspace{3ex}\noindent
{\em Optimal Scheduling Algorithm for Distributed Memory Machines},
Sekhar Darbha and Dharma P. Agrawal, North Carolina State University.

%86 032
\vspace{3ex}\noindent
{\em An Efficient Algorithm for Partitioning of Parallel Programs for 
Near-Optimal Scheduling}, Huade Li,
Piyush Maheshwari and Hong Shen, Griffith University.

%71 032
\vspace{3ex}\noindent
{\em The Effect of Inter-process Communication on Scheduling in 
Multiprogrammed Distributed Memory Systems},
Shikharesh Majumdar and Yiu Ming Leung, Carleton University.

%92 032
\vspace{3ex}\noindent
{\em Design of an Application Development Toolkit for HPF/Fortran 90D},
Manish Parashar, Salim Hariri, Tomasz Haupt and Geoffrey C. Fox,
Syracuse University.

%64 033
\vspace{3ex}\noindent
{\em GAPPE: Graphical Animation of Parallel Program Execution}
Alfred C. K.  Heng, Wentong Cai and Shu Fei Chia,
Nanyang Technological University, Singapore.



\vspace{4ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 3:30 PM - 4:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Afternoon Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf THURSDAY, DECEMBER 29}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 4:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 11: Software IV }\\
{{\bf Chair: }{Ajay Gupta, Western Michigan University }} \\
\end{center}

%4-6PM
%Software IV
%Chair:   

%67 033
\vspace{1ex}\noindent
{\em Compiling Irregular Programs for Distributed Memory Architectures},
Raja Das and Joel Saltz, University of Maryland-College Park.


%61 033
\vspace{3ex}\noindent
{\em Advanced Parallel Usage Analysis},
M. Manjunathaiah and D. Nicole, University of Southampton.


%53 033
\vspace{3ex}\noindent
{\em PRETSEL - A Parallel Real Time Specification Language for Real Time 
Systems on Parallel Computers},
Melissa Benincasa, Alok N. Choudhary, Vijay Gehlot,
Richard Metzger and Bhagirath Narahari,
Syracuse University.

%49 033
\vspace{3ex}\noindent
{\em Techniques for Compiling and Executing HOF Programs on Shared 
Memory and Distributed Memory Parallel Systems},
Larry Meadows, Vince Schuster, Zeki Bozkus,
Doug Miles and Mark Young, The Portland Group, Inc.


%43 033
\vspace{3ex}\noindent
{\em A Restructuring Compilation Method for the Xputer Paradigm},
K. Schmidt and R. W. Hartenstein, University of Kaiserslautern-Germany.


%4978 033
\vspace{3ex}\noindent
{\em Declarative  Programming on PARAM},
Manish Gupta and Vijay Chandru,
Indian institute of Science.

%11 033
\vspace{3ex}\noindent
{\em Parallelization of Loops with Affine Dependencies},
Patrick M. Lenders, University of New England-Austrailia.


%91 033
\vspace{3ex}\noindent
{\em Toward Scalable Parallel Software: Interfacing to non-von Neumann 
Programming Environments},
George K. Thiruvathukal and Thomas W. Christopher, R. R. Donelley and Sons, Co.



\vspace{6ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 6:00 PM - 8:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Dinner Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf THURSDAY, DECEMBER 29}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 8:00 PM - 10:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 12: Applications III }\\
{{\bf Chair: }{M. Ashraf Iqbal, Engineering University-Pakistan.}} \\
\end{center}

%8-10PM
%Applications III
%Chair:   

%4971 034
\vspace{3ex}\noindent
{\em An Interleaved Systolic Adaptive Architecture for Video
Ghost Elimination},
J. Thomas and S. Balakrishnan,
Indian Institute of Science.

%16 034
\vspace{3ex}\noindent
{\em Performance Analysis of Task Farming Programs in Heterogeneous 
Multi-User Environments},
Thomas Schnekenburger, Technische Universitaet Muenchen.


%123/4980 034
\vspace{3ex}\noindent
{\em Parallel I/O Access of Multiversion Data Structures},
Peter J. Varman, Rice University
and  Nanyang Technical University, Singapore and
Rakesh M. Verma, University of Houston.


%4935  034
\vspace{3ex}\noindent
{\em Multi-Installment Load Distribution Strategy in Networks with 
Communication Delays}, 
V. Bhardwaj, D. Ghose and V. Mani,
Indian Institute of Science.

%4956 034
\vspace{3ex}\noindent
{\em Parallelization of Multiblock Euler code AMES},
Lakshmi Soundararajan, K. Murali Krishna and K. P. Singh,
Aeronautical Development Agency.

%38 011
\vspace{3ex}\noindent
{\em Experimental Studies of Fine Grain Reconfigurable Architectures},
R. S. Bajwa, R. Kasamsetty, R. M. Owens and M. J. Irwin,
Pennsylvania State University.

%62 034
\vspace{3ex}\noindent
{\em A Platform to Study Dynamic Load Balancing Functions for Parallel 
Logic Systems},
J. Briat, S. E. Kannat, J. P. Kitajima and E. Morel, LGI-IMAG-INPG-France.

%130 034
\vspace{3ex}\noindent
{\em Exploiting Neural Network Parallelism},
Suthiksn Kumar, David Wo, M. Palaniswami
and Kevin Forward, University of Melbourne-Australia.



\vspace{6ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 10:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Adjourn for the day}\\
\end{center}



\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf FRIDAY, DECEMBER 30}\hspace*{0.2in}}


\vspace{3ex}

\fbox{{\hspace*{0.2in}\bf 8:30 AM - 9:30 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Keynote Address 4: }{\em System Architectures for High Performance Computing in the
1990s}\\ { Tilak Agerwala, IBM}\\

\vspace{4ex}

\fbox{{\hspace*{0.2in}\bf 9:30 AM - 10:00 AM}\hspace*{0.2in}}\\
\ \ \\
{\bf Morning Break}\\
\ \ \\
\ \ \\

\fbox{{\hspace*{0.2in}\bf 10:00 AM - 12:00 Noon}\hspace*{0.2in}}\\
\  \\
{\bf Session 13: Architecture IV }\\
{\bf Chair: }{R. Srinivasan, National Aerospace Laboratories.} \\
\end{center}


%December 30
%
%10-12
%Architecture IV
%Chair:    DR. R. SRINIVASAN, NATIONAL AEROSPACE LABORATORIES, BANGALORE

%4909  041
\vspace{1ex}\noindent
{\em Petersen-Twisted Cube: A New Multiprocessor Interconnection Network},
M. P. Sebastian, Lawrence Jenkins and P. S. Nagendra Rao,
Indian Institute of Science.


%66 041
\vspace{3ex}\noindent
{\em Transputer-based Embedded Parallel Processing in Ground Systems 
for Satellite Telemetry},
Tushar K. Hazra and Bhavana Singh, Martin Marietta Services, Inc.

%4949 041
\vspace{3ex}\noindent
{\em A  New Issue Method to Conserve Instruction Bandwidth},
Vinod G. Kulkarni and M. R. Bhujade,
Indian Institute of Technology, Bombay.


%27 041
\vspace{3ex}\noindent
{\em EQUALS - The Next Generation},
Owen Kaser, University of New Brunswick,
C. R. Ramakrishnan, SUNY Stony Brook and
R. C. Sekar, Bellcore.


%4944  041
\vspace{3ex}\noindent
{\em Performance Comparison of Various Latency Tolerant Architectures},
Swaminathan Ramany, University of Saskatchewan, Canada and
K. Gopinath, Indian Institute of Science.

%4941 041
\vspace{3ex}\noindent
{\em Synthesis of Energy Efficient Configurable Processor Arrays},
V. Viswanathan and S. Ramanathan, Indian Institute of Science.

%25 041
\vspace{3ex}\noindent
{\em Scalable Expanders from Finite Geometries},
Rama K. Govindaraju and Mukkai S. Krishnamoorthy,
Rensselaer Polytechnic Institute.

%41 041
\vspace{3ex}\noindent
{\em Using DPUs Interrupting Messages in Network Computing},
David M. Arnow, Brooklyn College.



\vspace{2ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 10:00 AM - 12:00 Noon}\hspace*{0.2in}}\\
\  \\
{\bf Industrial Track 1 }{ (TBA)}\\
\end{center}




\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf FRIDAY, DECEMBER 30}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 12:00 Noon - 1:30 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Lunch Break}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 1:30 PM - 3:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 14: Algorithms III }\\
{{\bf Chair: }{Ramesh Rao, University of California, San Diego.}} \\
\end{center}

%130-330
%Algorithms III
%Chair:   


%104 042
\vspace{1ex}\noindent
{\em Efficient Parallel R-tree Algorithm},
Dipak Pravin Doctor and Hal Sudborough,
University of Texas at Dallas.

%45 042
\vspace{2ex}\noindent
{\em Synchronization-Based Parallelization},
A. Jayawardena and Patrick Lenders,
University of New England-Australia.

%129 042
\vspace{2ex}\noindent
{\em A Parallel Algorithm for the Calculation of Kronecker Products, etc.}
R. J. White and N. Sharda,
Victoria University of Technology-Australia and
C. Osborne, Monash University, Clayton, Australia.

%125 042
\vspace{2ex}\noindent
{\em A Parallel Random Search Global  Optimization Techniques},
K. Deep, Central Building Research Institute, Roorkee and
D. J. Evans, Loughborough University of Technology.

%88 042
\vspace{2ex}\noindent
{\em Primitives for Problems using Hierarchical Algorithms on Distributed 
Memory Machines},
Sanjay Goil, Syracuse University.

%87 042
\vspace{2ex}\noindent
{\em Developing Self-Stabilizing Coloring Algorithms via Systematic 
Randomization},
Sandeep K. Shukla, Daniel J. Rosenkrantz and S. S. Ravi,
State University of New York, Albany.

%47 042
\vspace{2ex}\noindent
{\em Parallel Construction of the Suffix Array},
C. H. Lee and I. W. Chan, National University of Singapore.

%2 042
\vspace{2ex}\noindent
{\em Performance Measurements of Parallel Algorithms for Linear 
Programming Problems},
Alfred Loo, Lingnan College-Hong Kong.
 


\vspace{1ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 1:30 PM - 3:30 PM}\hspace*{0.2in}}\\
\  \\
{\bf Industrial Track 2 }{ (TBA)}\\
\end{center}

\vspace{2ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 3:30 PM - 4:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Afternoon Break}\\
\end{center}

\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf FRIDAY, DECEMBER 30}\hspace*{0.2in}}\\
\end{center}

\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 4:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Session 15: Applications IV }\\
{{\bf Chair: }{Ian Foster, Argonne National Laboratories.}} \\
\end{center}

%4-6PM
%Applications IV
%Chair:   

%4957 043
\vspace{1ex}\noindent
{\em Parallel Implementation of the Three Dimensional Turbulent Viscous 
Flow Code VASBI},
Biju Uthup, Aeronautical Development Agency, Bangalore,
K. Rajesh, Bhabha Atomic Research Center, Bombay and
S. M. Deshpande, Indian Institute of Science.

%70 043
\vspace{2ex}\noindent
{\em An Experimental Study of the Effects of Heterogeneity and Data 
Partitioning on the Performance of Parallel Applications},
Anantha K. Bangalore and Daniel A. Menasce, George Mason University.

%4912  043
\vspace{2ex}\noindent
{\em The Matvec Library for Data Parallel Computing 
and its Applications in Parallelization of CFD Algorithms},
G. M. Shroff, Indian Institute of Technology, New Delhi,
A. Mukhopadhyay, S. H. Rao  and
R. K. Mansharamani, Tata Research Development and Design Centre, Pune.

%18 043
\vspace{2ex}\noindent
{\em Implementation and Performance Evaluation of Massively Parallel 
Algorithms for Block Updating Least Squares},
Erricos J. Kontoghiorghes and Elias Dinenis, City University,  London.

%20 043
\vspace{2ex}\noindent
{\em The Porting of Parallel Applications from Transputer Based Machines 
to the Intel Paragon Supercomputer},
W. J. Cosshall,
Swinburne University of Technology and
I. Morrison, University of Melbourne.

%4923 043
\vspace{2ex}\noindent
{\em Hierarchical Censored Production Rules: Some Avenues for Parallelization},
Renu Varshneya and K. K. Bharadwaj, Jawaharlal Nehru University, New Delhi.

%4933  043
\vspace{2ex}\noindent
{\em A Step Towards User Independent Image Processing
Operating Environment for Distributed Processing},
Haresh S. Bhatt and C. V. S. Prakash,
Space Applications Center, Ahmedabad and
A. K. Aggarwal, Gujarat University, Ahemdabad.

%3 043
\vspace{2ex}\noindent
{\em Protocol Support for Application in VISTAnet Gigabit Network},
Raj K. Singh, Stephen G. Tell and Shaun J. Bharrat,
University of North Carolina.



\vspace{3ex}

\begin{center}
\fbox{{\hspace*{0.2in}\bf 4:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\  \\
{\bf Industrial Track 3 }{ (TBA)}\\
\end{center}

\vspace{3ex}


\begin{center}
\vspace{1ex}
\fbox{\hspace*{0.2in}{\bf 6:00 PM : Contributed Sessions End}\hspace*{0.2in}} \\
\vspace{1ex}
\end{center}


\newpage
\begin{center}
\fbox{\hspace*{0.2in}{\large\bf SATURDAY, DECEMBER 31}\hspace*{0.2in}}
\end{center}

\begin{center}
\fbox{\hspace*{0.2in}{\bf 9:00 AM - 1:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Tutorial 3}\\
{{\em Parallel Programming in Fortran M}}\\
\vspace*{0.1in}
    { Ian Foster\\
         Argonne National Laboratories} 
\end{center}

\noindent
{{\bf Description:}} Fortran M --- M for Modular --- 
is a small extension of Fortran 77 for
task-parallel programming.  Fortran M has object-oriented features and
provides compile-time guarantees of deterministic execution.
Compilers are available for many parallel and networked computers.
The tutorial will provide an introduction to programming in Fortran M,
focusing on the requirements of scientific and engineering
applications.

\noindent
{\bf Lecturer:}
Ian Foster received his Ph.D. from Imperial College in Computer Science
in 1988.  In 1989, the Strand programming system that he designed was
awarded the British Computer Society's award for technical innovation.
He is currently a Scientist in the Mathematics and Computer Science
Division of Argonne National Laboratory.  His latest book, ``Designing
and Building Parallel Programs," is being published simultaneously by
Addison-Wesley and on the World Wide Web.


\vspace*{0.4in}
\begin{center}
\fbox{\hspace*{0.2in}{\bf 2:00 PM - 6:00 PM}\hspace*{0.2in}}\\
\ \ \\
{\bf Tutorial 4}\\
{{\em Scalability of Parallel Systems}}\\
\vspace*{0.1in}
    { H. Venkateswaran\\
         Georgia Institute of Technology} 
\end{center}

\noindent
{{\bf Description:}} 
A parallel system is an application-architecture combination.
Scalability is a term that is often used to signify the ``goodness" of
parallel systems. A good understanding of this notion may be used to:
select the best architecture platform for an application domain,
predict the performance of an application on a larger configuration
of an existing architecture, and glean insight on the interaction between an
application and an architecture to understand the
scalability of other application-architecture pairs.
In this tutorial, we present a survey of metrics used to capture this
notion; the merits and demerits of these metrics; the factors
that lead to overheads in a parallel system; the techniques such as 
experimentation, simulation, and analytical modeling used in scalability
studies; and recent advances in understanding the scalability of parallel
systems.


\noindent
{{\bf Lecturer:}} 
H. Venkateswaran received his Ph.D. from the University of Washington,
Seattle in 1986. He is currently an Associate Professor in the
College of Computing at Georgia Institute of Technology, Atlanta. 
His primary research interests are in computational complexity theory
and parallel computation.  His research interests in parallel computation
concerns both theoretical and practical issues. He is a co-principal
investigator in a project that studies the impact of architectural
features on the performance of parallel algorithms.



\newpage
\begin{center}
\fbox{{\hspace*{0.2in}\large\bf LOCATION}\hspace*{0.2in}}
\end{center}
\vspace{2ex}


\noindent
{\bf About Bangalore:}
The venue for the First International Workshop on
Parallel Processing is the city of Bangalore. Bangalore is the capital
of the state of Karnataka and is the fifth largest city in India.
It is about 250 Kms from Madras and is about 800 Kms from Bombay.
Situated at an altitude of approximately 1000 Meters above sea level,
Bangalore has a population of over three million people. The
city is home to the Indian Institute of Science,
many aerospace and high technology industries including the 
Center for Development of Advanced Computing and is
often called the Silicon valley of India. The city's
prominent buildings include the Vidhana Soudha which is the
Legislative building and the palace of the maharaja of Mysore. From 
Bangalore many nearby historic and
archeological sites can be easily reached.

\vspace{2ex}
\noindent
{\bf Visa and Passports:}
All participants who are not citizens of India
must obtain a valid visa from Indian Consulates or High Commissions.
The procedure may take some time, check with your travel consultant
in advance.


\vspace{2ex}
\noindent
{\bf Currency:}
The currency is the Indian Rupee.
The conversion rate at the time of this publication is 1
US \$ to Rs. 31.50. Credit cards are accepted in most luxury hotels but
not in most commercial establishments.
The Reserve Bank of India may have certain restrictions on converting
Rupees to other currencies. For details, check with an  
Indian Consulate or your travel consultant.

\vspace{2ex}
\noindent
{\bf Time and Weather:}
The Indian Standard Time(IST) is 5 1/2 hours 
ahead of the Greenwich Mean Time(GMT)
and is 13 1/2 hours ahead of the U. S. Pacific Standard Time(PST).
In December/January the climate
is mildly tropical with temperatures averaging about 22
degrees Celsius (approx. 70 degrees Fahrenheit) during the day
and it is about 14 degrees Celsius (approx. 55 degrees
Fahrenheit) during the night.

\vspace{2ex}
\noindent
{\bf Travel:}
Many international carriers fly to India.
Since Bangalore does not have
an international airport one has to fly into Bombay, New Delhi or
Madras and connect to Bangalore. Indian Airlines and several private
airlines connect Bangalore with major cities on a daily basis. It is
advisable to make reservations early as travel is heavy during the
months of December and January. The workshop does not endorse any
travel agency, however, to assist international travelers with late
reservations a block of seats has been reserved. You may contact
Globalink Travels in the Los Angeles area at  818-907-8302 (FAX) and
818-972-9525 (VOX) for details.


\vspace{2ex}
\noindent
{\bf Accommodation:}
The Oberoi is offering a special rate of US \$ 129.50 (per night, single
or double) for workshop
participants. The rate includes all taxes.
The Oberoi is a deluxe hotel situated on
Mahatma Gandhi road, which is the city's most famous promenade. The
hotel has a 24 hour business center which has a comprehensive
range of facilities, including offices for private use and a board
room for select meetings.
The airport is less than 10 Kms from the hotel.
The cost of the ride to or from the
airport can vary, and a one-way taxi ride will cost around US \$ 6 
including tip.

\vspace{2ex}
\noindent
Additional information about Bangalore(as well as places of interest
in the state of Karnataka and in India) can be found on the World Wide Web (WWW)
under:\\
\hspace*{1in}http://spiderman.bu.edu/misc/karnataka/tourism/index.html\\
\hspace*{1in}http://spiderman.bu.edu/misc/karnataka/cities/bangalore/index.html\\
\hspace*{1in}http://spiderman.bu.edu/misc/karnataka/index.html\\
\hspace*{1in}http://enuxsa.eas.asu.edu/$\sim$sridhar/places/india.html\\



\newpage
\begin{center}
\fbox{\hspace*{0.2in}{\large\bf IWPP '94 HOTEL RESERVATION}\hspace*{0.2in}} \\
\end{center}

\noindent
The Workshop will be held at the following address.
\begin{center}
The Oberoi \\
37-39, Mahatma Gandhi Road\\
Bangalore 560 001, India\\
Tel: 91-80-558 5858\\
Fax: 91-80-558 5960
\end{center}
A block of rooms has been reserved for the workshop participants.
The special IWPP '94 rates are US \$ 129.50(per night, single or double).
This rate includes all applicable taxes at the time of
this publication. Please make room reservations directly with the hotel
or through Datalead Worldwide Reservations System.
Some toll free numbers are listed below. Please check with your
travel consultant for additional
Datalead reservations information.
While making reservations use the group name ``International
Workshop on Parallel Processing.''
The cut off date for reservations is December 10. 
Since December is a busy time for travel in India, you may want to
reserve your room in advance.\\

		\centerline{{\bf Datalead Reservations Worldwide Telephone Numbers}}

\noindent
USA \& CANADA:		1-800-5-OBEROI	toll free,
  New York City		752-6565	local.


\noindent
EUROPE:
United Kingdom		0800 515 517	toll free,
Germany			0130 82 42 22	toll free,
Belgium			078,11 04 71	toll free,
Denmark			80 01 85 93	toll free,
France			05 90 86 07	toll free,
Netherlands		06 022 9702	toll free,
Norway			050 11017	toll free,
Spain			900 200104	toll free,
Sweden			020 792922	toll free,
Switzerland		155 2737	toll free,
Italy			1678-25107	toll free.


\noindent
ASIA/PACIFIC:
Australia		008 802 509 	toll free,
  Sydney		233 4016	local,
Hong Kong		800 2595	toll free,
Japan			0120 025 725	toll free,
  Tokyo			5210 5135	local,
Malaysia		800 1081	toll free,
New Zealand		0800 44 1647	toll free,
Singapore		737 0005	local.




\vspace*{0.6in}
\begin{center}
\fbox{\hspace*{0.2in}{\large\bf IWPP '94 REGISTRATION NOTES}\hspace*{0.2in}}\\
\end{center}

\noindent
{Written requests for workshop fee refunds must be received by
your Finance Co-Chair by no later 
than November 25. Refunds are subject to a US \$25 
(Rs. 250 for tutorials) 
processing fee. All no-show registrations will be billed in full. 
Registrations after November 26 will be accepted on-site only.}

\noindent
{The registration desk will be open for on-site registration
from 8 AM to 6 PM during December  26 -  December 30 and from
8 AM to 12 Noon on December 31.}

\noindent
{Major credit cards will be accepted on-site for Workshop registration.}

\newpage
\vspace*{-0.5in}
\begin{center}
\fbox{\hspace*{0.3in}{\large\bf ADVANCE REGISTRATION FORM}\hspace*{0.3in}}\\
\ \ \\
{\bf IWPP '94 
%- First International Workshop on Parallel Processing
} \\ 
{\bf December 26-31, 1994} \hspace*{0.1in}
{\bf The Oberoi, Bangalore, India}\\ 
\vspace*{0.2in}
\end{center}

\noindent
{\bf Please Print:}\\
\ \ \\
\vspace*{-1.8ex}
{\em Name:}\hrulefill\\
{\tiny\hspace*{1in} Last/Family \hfill First \hfill M.I. \hfill Name on Badge}\\

\vspace*{-3ex}
\noindent
{\em Company/University:}\hrulefill\\
{\em Address/Mail Stop:}\hrulefill\\
{\em City/State/Zip/Country:}\hrulefill\\
{\em Daytime Number:}\hrulefill {\em Fax Number:}\hrulefill\\
{\em IEEE Membership Number:}\hrulefill {\em E-Mail:}\hrulefill\\
{\em Dietary needs:}\ \ \ \ \ \ \ \ \ \ {\em Vegetarian}\hrulefill {\em Spicy}\hrulefill


\noindent
{\bf Please Circle Appropriate Fees:}\\
\ \ \\
\vspace{-2ex}
{\bf $\cdots$ Workshop Registration Fees:}\\
\hspace*{-0.1in}\begin{tabular}{lrcrcrc}
&\hspace{0.00in}& \underline{IEEE-Member} & \hspace{0.00in} & 
	\underline{Non-Member} & \hspace{0.00in} & \underline{Student}\\
Advance Registration {\small (Until Nov. 25)} & & US \$ 80 & & US \$ 100 
	& & US \$ 80 \\
Late/Onsite Registration {\small (After Nov. 26)} & & US \$ 100 & & US \$ 125 
	& & US \$ 100\\
\end{tabular}\\
\ \ \\
{The registration fee includes a copy of the hardcover proceedings,
lunch, refreshments \& dinner on December 27, 28 \& 29 and
lunch \& refreshments on December 30.
All Workshop activities will be held at the Oberoi, a 5 star hotel.
Scholarships to full time students currently enrolled in
universities in India are available. For details contact
Professor Ravi Kumar at {\em rkumar@ee.iitd.ernet.in}.
These scholarships are not available to students attending
schools outside India.}\\

\vspace*{-2ex}
\noindent
{\bf $\cdots$ Tutorial Registration:} \\
\hspace*{0.2in}\hrulefill Tutorial 1: HPF...
\hspace*{0.2in}\hrulefill Tutorial 2: PVM Prog....  \\
\hspace*{0.2in}\hrulefill Tutorial 3: Fortran M...\hspace*{0.18in}
\hspace*{0.2in}\hrulefill Tutorial 4: Scalability of...\hspace*{0.135in}  \\
{\bf $\cdots$ Tutorial Fees:} (Fee per tutorial)\\
\hspace*{-0.1in}\begin{tabular}{lrcrcrc}
& \hspace{0.0in} & \underline{IEEE-Member/Student} & \hspace{0.0in} & 
	\underline{Non-Member} & \hspace{0.0in} \\
Advance Registration {\small (Until Nov. 25)} & & Rs. 500 & &
	Rs. 600 & \\
Late/Onsite Registration {\small (After Nov. 26)} & & Rs. 750 & & 
	Rs. 900 & \\
\end{tabular}

\noindent
{\bf Total Amount Enclosed:} \hrulefill\hspace*{2in}\\
{{Payment must be enclosed. Please make cheques payable to 
International Workshop on Parallel Processing.
All cheques MUST be either in U.S. Dollars drawn on a U.S. Bank or
in Indian Rs. drawn on an Indian Bank. Participants
\underline{currently residing in India}
may pay in Indian Rs., all others (including NRIs) must pay in US Dollars.
The exchange rate is set at US \$1 = Indian Rs. 31.50.
All fees must be converted using this rate.}}
\ \ \\
\ \ \\
\noindent
{\bf Please Mail to:}\hspace*{0.1in}
\begin{tabular}{lcl}
IWPP '94 c/o Suresh Chalasani & \hspace*{0.5in} & IWPP '94 c/o A. K. P. Nambiar\\
ECE Dept., 1415 Johnson Dr.& {\bf or to:} & C-DAC\\
University of Wisconsin & & 2/1, Brunton Road\\
Madison, WI 53706-1691, USA   & & Bangalore, 560025, India \\
Email: suresh@ece.wisc.edu & & Email: nambiar@cdacb.ernet.in\\
\end{tabular}\\
\ \ \\
\noindent
{ Participants currently residing in India are requested to send their 
registration material
to Mr. Nambiar, all others are requested to send them to Professor Chalasani.}

\begin{center}
\  \ \\
{\bf See Page 22 for Registration Notes}
\end{center}

\newpage
\ \ \\


\end{document}

-- 
Dhabaleswar K. Panda, Asst. Professor        e-mail: panda@cis.ohio-state.edu
Dept. of Computer and Information Science    Office: (614) 292-5199 (Tel)
Ohio State University, Columbus, OH 43210-1277, USA. (614) 292-2911 (Fax)

