Newsgroups: comp.parallel.mpi
From: talbi@lifl.fr (El-ghazali.Talbi)
Subject: Call for papers (load balancing and scheduling)
Keywords: load balancing, scheduling
Organization: Laboratoire d'Informatique Fondamentale de Lille - France
Date: 2 Dec 1996 17:36:50 GMT
Message-ID: <57v43i$kdf@netserver.univ-lille1.fr>



                     C A L L   F O R   P A P E R S
                     =============================


        ****************************************************             
         Technical Session on Load Balancing and Scheduling
        ****************************************************

                            to be held in

      International Conference on Parallel and Distributed Processing
                  Techniques and Applications (PDPTA'97)

                          June 30 - July 2, 1997
                          Las Vegas, Nevada, USA


The 1997 International Conference on Parallel and Distributed Processing
Techniques and Applications (PDPTA'97) will be held in Las Vegas,
Nevada, June 30 - July 2, 1997.
The last conference (PDPTA'96) had research contributions from 37
countries.  It is hoped that PDPTA'97 will also have a strong
international flavor.  For information on the last two PDPTA conferences
(PDPTA'95 and PDPTA'96), refer to: http://www.cps.udayton.edu/~pan/pdpta. All accepted papers will be published in the conference
proceedings.


Session Chair : El-ghazali TALBI (LIFL / University of Lille 1 - France)
=============

Scope and objectives of the session :
====================================
In the design of parallel applications, programming environments and distributed operating systems, the strategy used for process (task, object, ...) allocation has a great impact on the system performances.  Most of the proposed allocation algorithms in the literature are based on heuristics, because of the impossibility to have a coherent global state of a distributed system and the time constraints of the process allocation decision making.

The objectives of this session is to give a review of the different research studies in this field. Allocation algorithms may be classified following the strategy used in the information exchange protocol to maintain the current state of a distributed system, and the process placement protocol to localize the destination of a process. The process migration mechanism may be used to redistributed the load.

We will focus on the adaptive dimension of scheduling algorithms. The proliferation of powerful workstations and fast communication networks with constantly decreasing cost/performance ratio have shown the emergence of heterogeneous workstations networks and clusters of processors as parallel platforms.
 These parallel platforms are generally composed of an important park of machines shared by many users. Load analysis of those platforms during long periods of time showed that only a few percentage of the available power was used. There is a substantial amount of idle time and therefore adaptive scheduling of parallel applications is essential.

SUBMISSION OF PAPERS:

      Prospective authors are invited to submit three copies of their
      draft paper (about 5 pages) to E-G. TALBI (address is given
      below) by the due date.  E-mail and Fax submissions are also
      acceptable.  The length of the Camera-Ready papers (if accepted)
      will be limited to 10 pages.  Papers must not have been
      previously published or currently submitted for publication
      elsewhere.

      The first page of the draft paper should include: title of the
      paper, name, affiliation, postal address, E-mail address,
      telephone number, and Fax number for each author.  The first
      page should also include the name of the author who will be
      presenting the paper (if accepted) and a maximum of 5 keywords.


PUBLICATION:

      The conference proceedings will be published by CSREA Press.
      It will be a multivolume set.  The proceedings will be available
      at the conference.
      

ORGANIZERS/SPONSORS:

      A number of university faculty members in cooperation with
      the Monte Carlo Hotel (conference division) will be organizing
      the conference.  The conference is sponsored by the Computer
      Science Research, Education, and Applications Tech. (CSREA) in
      cooperation with the North American Transputer Users Group
      (NATUG), the Computer Vision Research and Applications Tech.
      (CVRA), the National Supercomputing Center for Energy and the
      Environment (USA), developers of high-performance machines and
      systems (pending) and related computer associations (pending.)


LOCATION OF CONFERENCE:

      The conference will be held in the Monte Carlo Resort and
      Casino hotel, Las Vegas, Nevada, USA.  This is a new hotel
      with excellent conference facilities and over 3000 rooms.
      The hotel is minutes from the Las Vegas airport with free
      shuttles to and from the airport.
      The hotel has many vacation and recreational attractions,
      including: casino, waterfalls, spa, kiddie pools, sunning
      decks, Easy River water ride, wave pool with cascades,
      lighted tennis courts, health spa (with workout equipment,
      whirlpool, sauna, ...), arcade virtual reality game rooms,
      nightly shows, snack bars, a number of restaurants, shopping
      area, ...  Many of these attractions are open 24 hours a day
      and most are suitable for families and children.
      The hotel's room rate is very reasonable ($79 + 8% tax) per
      night for the duration of the conference.

      The hotel is minutes from other Las Vegas attractions (major
      shopping areas, recreational destinations, fine dining and
      night clubs, free street shows, ...).

      For the benefit of our international colleagues: the state of
      Nevada neighbors with the states of California, Oregon, Idaho,
      Utah, and Arizona.  Las Vegas is only a few driving hours away
      from other major cities, including: Los Angeles, San Diego,
      Phoenix, ...


EXHIBITION:

      An exhibition is planned during the conference.  We have reserved
      20+ exhibit spaces.  Interested parties should contact
      H. R. Arabnia (address is given below).
      All exhibitors will be considered to be the co-sponsors of
      the conference.  Each exhibitor will have the opportunity to
      include a two-page description of their latest products in the
      conference proceedings (if submitted by May 19, 1997).


IMPORTANT DATES:

      February 3, 1997 : Draft papers (5-page) due
      April  8, 1997 : Notification of acceptance
      May 19, 1997 : Camera-Ready papers & Preregistration due
      June 30, July 1, July 2: PDPTA'97 Conference

      All accepted papers are expected to be presented at the conference.


SESSION CONTACT:

          Dr. El-ghazali TALBI
          (PDPTA Session "Load Balancing and Scheduling" Chair)
          Laboratoire d'Informatique Fondamentale de Lille
          Universit de Lille 1
          Bat. M3  59655 Villeneuve d'Ascq FRANCE
          Tel: (33 3) 20 43 45 13
          Fax: (33 3) 20 43 65 66
          E-mail: talbi@lifl.fr


CONFERENCE CONTACT:

          Professor Hamid R. Arabnia
          (PDPTA General Chair)
          The University of Georgia
          Department of Computer Science
          415 Graduate Studies Research Center
          Athens, Georgia 30602-7404, U.S.A.
          Tel: (706) 542-3480
          Fax: (706) 542-2966
          E-mail: hra@cs.uga.edu

LOCAL ARRANGEMENT CHAIRS:

          Professor Kia Makki
          Department of Computer Science
          University of Nevada Las Vegas
          Las Vegas, Nevada 89154-4019, USA
          kia@koko.cs.unlv.edu

          Professor Niki Pissinou
          Center For Advanced Computer Studies
          University of Southwestern Louisiana
          Lafayette, LA 70508, USA
          pissinou@cacs.usl.edu


PUBLICITY CHAIRS:

          Professor Yi Pan
          Department of Computer Science
          University of Dayton
          Dayton, OH 45469-2160, USA
          pan@cps.udayton.edu
          Tel: (513) 229-3807
          Fax: (513) 229-4000

          Professor Albert Y. Zomaya
          Parallel Computing Research Lab
          Department of Electrical & Electronic Engineering
          University of Western Australia
          Western Australia 6907
          zomaya@ee.uwa.edu.au
          Tel: +61-9-380-3875
          Fax: +61-9-380-1088


                                   http://www.cps.udayton.edu/~pan/pdpta




