Newsgroups: comp.arch,comp.parallel.pvm,comp.parallel.mpi,comp.org.acm,comp.org.ieee,comp.sys.super
From: jayasim@maine.cis.ohio-state.edu (D Jayasimha)
Subject: Advance Program- Int'l Conf on High Perf Computing (HiPC '96)
Organization: The Ohio State University, Department of Computer and Information Science
Date: 27 Aug 1996 19:36:53 -0400
Message-ID: <5000qlINN18c@maine.cis.ohio-state.edu>


         3rd International Conference on High Performance Computing

                  December 19-22, 1996 - Trivandrum, India.

                         Held in Cooperation with
       IEEE Computer Society Technical Committee on Parallel Processing
                             and ACM SIGARCH


                                  CONTENTS


   * ACKNOWLEDGEMENTS

   * CONFERENCE ORGANIZATION

   * CONFERENCE OVERVIEW

   * THURSDAY, DECEMBER 19

   * FRIDAY, DECEMBER 20

   * SATURDAY, DECEMBER 21

   * SUNDAY, DECEMBER 22

   * LOCAL INFORMATION

   * CONFERENCE REGISTRATION FORM

   * HOTEL RESERVATION FORM

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                              ACKNOWLEDGEMENTS

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THE ORGANIZING COMMITTEE OF HiPC '96 GRATEFULLY ACKNOWLEDGES THE SUPPORT AND
PARTICIPATION OF THE FOLLOWING ORGANIZATIONS:

            Centre for Development of Advanced Computing, India

                    Infosys Technologies Limited, India

               Silicon Graphics Systems (India) Pvt. Limited

                           Technopark, Trivandrum

                  Tata Information Systems Limited, India

                     Digital Equipment (India) Limited

                         Tata Elxsi (India) Limited

   CSIR Centre for Mathematical Modelling and Computer Simulation, India

             Supercomputer Education and Research Centre, India

            Tata Institute of Fundamental Research (TIFR), India

                   Indian Institute of Science, Bangalore

                      Indian Institutes of Technology

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                                ORGANIZATION

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GENERAL CO-CHAIRS
Viktor K. Prasanna
University of Southern California

Vijay P. Bhatkar
Centre for Development of Advanced Computing, Pune

PROGRAM CHAIR
Sartaj Sahni
University of Florida

LOCAL ARRANGEMENTS CHAIR
G. Vijaya Raghavan
Technopark

LOCAL ORGANIZATION COMMITTEE
Ananthakrishnan
S. Gopakumar
K. G. Satheesh Kumar
A. K. Pujari
E. E. Rajkumar
N. A. P. Thampi
Simon Zachariah

EXHIBITS CO-CHAIRS
S.K. Nandy
Indian Institute of Science

K.G. Satheesh Kumar
Technopark

PROCEEDINGS CHAIR
John K. Antonio
Texas Tech University

PUBLICITY CO-ORDINATORS
D.N. Jayasimha
Intel Corp., Santa Clara

Afonso Ferreira
CNRS-LIP, France

Cho-Chin Lin
National I-Lan Institute of Agriculture and Technology, Taiwan, ROC

FINANCE CO-CHAIRS
A. K. P. Nambiar
Centre for Development of Advanced Computing, Bangalore

Ajay Gupta
Western Michigan University

REGISTRATION CO-CHAIRS
Ramesh Rao
University of California, San Diego

C.P. Ravikumar
Indian Institute of Technology, Delhi

STEERING COMMITTEE
Arvind, MIT
Vijay Bhatkar, C-DAC
Ian Foster, Argonne National Labs.
Anoop Gupta, Stanford University
David Kahaner, Asian Technology Information Program, Japan
Lionel Ni, Michigan State University
S.S. Oberoi, Dept. of Electronics, Government of India
Lalit M. Patnaik, Indian Institute of Science
Viktor K. Prasanna, USC, Chair
Josi D. P. Rolim, University of Geneva
Sartaj Sahni, University of Florida
Vaidy Sunderam, Emory University
Satish Tripathi, University of Maryland
David Walker, Oak Ridge National Labs.
K.S. Yajnik, CSIR Centre for Mathematical Modelling and Computer Simulation
Albert Y. Zomaya, University of Western Australia

NATIONAL ADVISORY COMMITTEE
N. Balakrishnan
Supercomputer Education and Research Centre,
Indian Institute of Science, Bangalore
Ashok Desai
Silicon Graphics Systems (India) Private Ltd.
H. K. Kaura
Bhabha Atomic Research Center
Hans H. Krafka
Siemens Communication Software Ltd.
Ashish Mahadwar
Microland Ltd.
Pradeep Marwaha
Cray Research International Inc.
Susanta Misra
Motorola India Electronics Ltd.
Som Mittal
Digital Equipment (India) Ltd.
N. R. Narayana Murthy
Infosys Technologies Ltd.
V. Rajaraman
Jawaharlal Nehru Centre for Advanced Scientific Research
S. Ramadorai
Tata Consultancy Services, Bombay.
Yogi Singh
Tata Information Systems Ltd.
G. S. Varadan
Software Technology Park, Bangalore

PROGRAM COMMITTEE
Mikhail Atallah, Purdue University
Prith Banerjee, University of Illinois
Silvano Barros, University of London, England
Francine Berman, UC San Diego
Pramod Bhatt, IIT, Delhi
Moreshwar Bhujade, IIT, Bombay
Suresh Chalasani, University of Wisconsin
Wen-Tsuen Chen, National Tsing Hua University
Yookun Cho, Seoul National University
Sajal Das, University of North Texas
Tim Davis, University of Florida
Eliezer Dekel, IBM, Israel
P.S. Dhekne, BARC
Iain Duff, Rutherford Appleton Laboratory, England
Afonso Ferreira, CNRS-LIP, France
R.K. Ghosh, IIT, Kanpur
Wolfang Giloi, GMD Lab., Germany
Mounir Hamdi, Hong Kong University of Science and Technology
C. T. Ho, IBM, Almaden
Oscar Ibarra, University of California, Santa Barbara
Mary Jane Irwin, Pennsylvania State University
S.S. Iyengar, Louisiana State University
D.N. Jayasimha, Intel Corp., Santa Clara
Anand Kumar, C-MMACS
J. Mohan Kumar, Curtin University of Technology, Australia
Vipin Kumar, University of Minnesota
Ten-Hwang Lai, Ohio State University
Sachin Maheshwari, IIT, Delhi
Kurt Maly, Old Dominion University
David Nassimi, New Jersey Institute of Technology
David Padua, University of Illinois
Krishna Palem, New York University
C. Pandu Rangan, IIT, Madras
Sanguthevar Rajasekaran, University of Florida
Sanjay Rajopadhyaye, IRISA, France
Vijaya Ramachandran, University of Texas
N. Ranganathan, University of South Florida, Tampa
Sanjay Ranka, University of Florida
Ranjan Sen, IIT, Kharagpur
Gautam Shroff, IIT, Delhi
R.K. Shyamasundar, TIFR
H.J. Siegel, Purdue University
Bhabani Sinha, ISI, Calcutta
Arun Somani, University of Washington
Per Stenstrom, Lund University, Sweden
Charles Weems, University of Massachusetts
Zhiwei Xu, Chinese Academy of Sciences, PRC
Tao Yang, University of California, Santa Barbara
Chung-Kwang Yuen, National University of Singapore
Albert Zomaya, University of Western Australia



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                            CONFERENCE OVERVIEW

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HiPC '96 PROGRAM SCHEDULE

The HiPC '96 events include contributed technical papers, keynote addresses,
a panel, exhibits, vendor presentations, and tutorials. Thursday through
Saturday will feature sessions for contributed papers, a panel discussion
and industrial track presentations, with a keynote address beginning the
proceedings of each day. The tutorials will be conducted on Sunday.

CONTRIBUTED PAPERS

There will be 78 contributed technical papers from 18 countries. They will
be presented in 12 technical sessions.

KEYNOTE ADDRESSES

Each day will begin with a keynote address:

Thursday, December 19:
"Distributed Applications on the Global Information Infrastructure"
K. Mani Chandy
California Institute of Technology

Friday, December 20:
"Scalable Parallel Computing at IBM: Past, Present and Future"
Marc Snir
IBM T. J. Watson Research Centre

Saturday, December 21:
"Efficient Access and Delivery of Images for the Digital Library"
Oscar Ibarra
Univerisity of California, Santa Barbara

In addition, the following keynote address has been tentatively scheduled
for Thursday afternoon:

"Whither MPP? A Look into the Future of High Performance Computing"
Greg Papadopoulos
SUN Microsystems

PANEL

"Supercomputers as a commodity: Can scientific and commercial computing be
performed on the same machine?"
The panel will discuss the burgeoning market for SMP (Symmetric
Multi-Processors) "servers" and its role in different types of computing.

Moderator: Arvind, MIT

Panelists:
Vijay P. Bhatkar, C-DAC
Rajiv Gupta, HP Labs
Kei Hiraki, University of Tokyo
Chris Jesshope, Masey University
Rishiyur S. Nikhil, DEC CRL
Greg Papadopoulos, SUN Microsystems
N. Radhakrishnan, US ARMY CEWES
Marc Snir, IBM T. J. Watson Research Centre

TUTORIALS

The following six tutorials will be held on Sunday. The duration of each
tutorial is half a day.

   * Mobile and Wireless Computing
   * Scalable Parallel Computer Architectures
   * High Performance Simulation: Possibilities and Pitfalls in
     Decomposition and Mapping
   * Object Oriented Parallel Programming
   * Recent Advances in Concurrent Object Oriented Programming
   * Why Systolic Arrays: The Real Answer

EXHIBITS/VENDOR PRESENTATIONS

Companies and R&D laboratories are encouraged to present their exhibits at
the meeting. In addition, a full day of vendor presentations is planned. For
details, companies are encouraged to contact the Exhibits/Vendor
Presentations Co-Chairs by September 30, 1996:

S.K. Nandy
Supercomputer Education and Research Centre
Indian Institute of Science
Bangalore 560012, India
Fax: +91 (80) 334 6648
Vox: +91 (80) 334 1811
Internet: nandy@cadl.iisc.ernet.in

K.G. Satheesh Kumar
Technopark
Technopark Campus
Trivandrum 695581, India
Fax: +91 (471) 417 971

HiPC '96 PROCEEDINGS

The proceedings will be published by the IEEE Computer Society Press.
The proceedings will also be available on the Web.

SOCIAL EVENTS

Refreshments will be served at several breaks throughout the day. In
addition, lunch will be provided on December 19, 20 and 21. There will be a
reception along with the Poster Session on Thursday evening. Following the
Poster Session a dinner event is planned.

REGISTRATION

The registration form can be found in this document. Note that the form
must be received by November 15, 1996 for advance registration. Registration
after November 15 will be accepted on-site only.

HiPC '96 LOCATION

The meeting will be held in Trivandrum. Information about Trivandrum and
surrounding areas can be retrieved from the Web using the URLs:
http://www.cs.cmu.edu/afs/cs/user/vipin/www/kerala.html or
http://www.granada.com/kerala/map



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                            THURSDAY, DECEMBER 19

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                               9:00AM-9:05AM
                              Opening Remarks
                             Viktor K. Prasanna
                              Vijay P. Bhatkar
                                Sartaj Sahni

                               9:05AM-10:05AM
                              Keynote Address

     "Dtributed Applications on the Global Information Infrastructure"
                               K. Mani Chandy
                     California Institute of Technology


                              10:30AM-12:30PM
                                Session I-A

                                Applications
                           Chair: Chris Jesshope
                              Masey University

A Genetic Algorithm for Assembling Optical Computers Using Faulty Optical
Arrays
C. P. Ravikumar, Augustine R. Thomas, and Abhay Gupta
Indian Institute of Technology, New Delhi

Comparison of Parallelisation Strategies for Simulation of Aerodynamics
Problems
Simon See Chong Wee
Silicon Graphics Ltd., Singapore

File Allocation for a Parallel Webserver
Rahul Simha, Bhagirath Narahari, Li Chen, and H-A. Choi
The George Washington University

Parallel Genetic Algorithms on PARAM for Conformation of Biopolymers
V. Sundararajan and A. S. Kolaskar
C-DAC, Pune

Parallelization of Solve in Direct Circuit Simulation on a Transputer Array
Yul Chu, Ausif Mahmood, and Donald J. Lynch
University of Bridgeport

Monte Carlo Device Simulation on PARAM
Ashwani Harkar, V. Sundararajan, A. D. Shaligram, and S. V. Ghaisas
C-DAC, Pune

Classification of Handwritten Alphanumeric Characters: A Fuzzy Neural
Approach
S. Annadurai and A. Balasubramaniam
Anna University



                              10:30AM-12:30PM
                                Session I-B

                             I/O and Compilers
                             Chair: M. Bhujade
                       Indian Institute of Technology
                                   Bombay

Impact of Delays in Parallel I/O System: An Empirical Study
C. R. Venugopal and S. S. S. P. Rao
Indian Institute of Technology, Bombay

Techniques for Increasing the Stream Capacity of a Multimedia Server
Divyesh Jadav and Alok Choudhary
Syracuse University

Compiling Object-Oriented Programs for Distributed Execution
Prakash K. Muthukrishnan, Barrett R. Bryant, and Amy E. Zwarico
University of Alabama at Birmingham

The RAID Configuration Tool
Peter Zabback, Jai Menon, and Jeff Riegel
IBM Almaden Research Center

Efficient Compilation of Concurrent Call/Return Communication in Actor-Based
Programming Languages
WooYoung Kim, Rajendra Panwar, and Gul Agha
University of Illinois at Urbana-Champaign

Integrating Concurrency and Object-Orientation Using Boolean, Access and
Path Guards
A. S. M. Sajeev
Monash University, Australia

Compilation to Parallel Programs from Constraints
Ajita John and J. C. Browne
University of Texas at Austin


                               2:00PM-3:00PM
                              Keynote Address

    "Whither MPP? A look into the Future of High Performance Computing"
                             Greg Papadopoulos
                              SUN Microsystems


                               3:30PM-5:30PM
                                Session II-A

                            Scientific Computing
                             Chair: Anand Kumar
                                  C-MMACS

Finite Element Calculations on the Parallel Computers Intel/Paragon, IBM
SP-2, and a Cluster of DEC-ALPHA Workstations
Astrid Watermann
Institute for Safety Research and Reactor Technology, Research Center Julich

Program-Level Control of Network Delay for Parallel Asynchronous Iterative
Applications
P. J. Joseph and Sriram Vajapeyam
Indian Institute of Science

Adaptive Integration Using Evolutionary Strategies
Elise deDoncker, Ajay Gupta, and Garrison Greenwood
Western Michigan University

Transpose Based Parallelization of T80 Weather Code on PARAM8600
Sanjay Kumar Agrawal and Pankaj Mehra
Indian Institute of Technology, Delhi

Finite Element Applications of Parallel Adaptive Integration Strategies
Elise de Doncker, Patricia Ealy, and Ajay Gupta
Western Michigan University

Distributed Computation of Inverse Dynamics of Robots
R. Rajagopalan and R. M. H. Cheng
Concordia University


                               3:30PM-5:30PM
                                Session II-B

                          Data and File Management
                              Chair: Simon Wee
                      Silicon Graphics Ltd., Singapore

DiET: A Distributed Extended Transaction Processing Framework
K. Hari Prasad, T. K. Nayak, and R. K. Ghosh
Indian Institute of Technology, Kanpur

BAG Real-Time Distributed Operating System
B. Tevfik Akgun, Ersoy Peksen, A. Emre Harmanci, Nadia Erdogan, and Gurhan
Menderes
Istanbul Teknik Universitesi

Bounded Dynamic Data Allocation in Distributed Systems
Oliver Theel and Henning Pagnia
Campus Universitaire de Beaulieux, France

Transparent Parallel Replication of Logically Partitioned Databases
Rekha Goel and Gautam M. Shroff
Indian Institute of Technology, New Delhi

A Distributed Directory Scheme for Information Access in Mobile Computers
J. Mohan Kumar, S. Venkatesh, and S. Panchanathan
Curtin University of Technology

Novel Parallel Join Algorithms for Grid Files
Salahadin Mohammed, Bala Srinivasan, and Phu Dung Le
Monash University


                               5:30PM-7:30PM
                        Reception and Poster Session

                                   7:30PM
                             Conference Banquet



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                            FRIDAY, DECEMBER 20

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                               9:00AM-10:00AM
                              Keynote Address

       "Scalable Parallel Computing at IBM: Past, Present and Future"
                                 Marc Snir
                      IBM T. J. Watson Research Centre

                             Industrial Track:
                        Invited Vendor Presentations
                        Industrial Track Co-Chairs:
                                 S.K. Nandy
                        Indian Institute of Science
                                    and
                            K.G. Satheesh Kumar
                                 Technopark

                              10:30AM-12:30PM
                         Industrial Track Session I
                                    TBA


                              10:30AM-12:30PM
                               Session III-A

                          Interconnection Networks
                            Chair: Jelena Misic
               Hong Kong University of Science and Technology

Congestion-Free Dilation 2 Embedding of Full Binary Trees on Star Graphs
D. K. Saikia, R. Badrinath, and R. K. Sen
Indian Institute of Technology, Kharagpur

Evaluation of a Mesh of Clos Wormhole Network
A. D. Pimentel and L. O. Hertzberger
University of Amsterdam, The Netherlands

Embedding a Ring in a Hypercube with Both Faulty Links and Faulty Nodes
Yu-Chee Tseng
Chung-Hua Polytechnic Institute, Taiwan

Embedding Arbitrary Trees in the Hypercube and the q-Dimensional Mesh
J. Gaber, B. Toursel, and G. Goncalves
Universite des Science et Technologies de Lillel, France

GSE: A Generalized Full-Access Multistage Interconnection Network with
Minimum Cost
Rajib K. Das and Nabanita Das
Indian Statistical Institute, Calcutta

The Generalized Hypercube-Connected-Cycle: An Efficient Network Topology
Srabani Sen Gupta, Debasish Das, and Bhabani P. Sinha
Indian Statistical Institute, Calcutta


                              10:30AM-12:30PM
                               Session III-B

                                 Compilers
                              Chair: R K Ghosh
                       Indian Institute of Technology
                                   Kanpur

Program Analysis for Page Size Selection
Aniruddha P. Bhutkar and K. Gopinath
Indian Institute of Science, Bangalore

Incremental Data Dependence Analysis
Praveen K. V., Sanjeev Aggarwal, and R. K. Ghosh
Indian Institute of Technology, Kanpur

A Communication Placement Framework with Unified Dependence and Data-Flow
Analysis
Ken Kennedy and Ajay Sethi
Rice University, Houston

Implementation of a Pattern-Matching Approach for Identifying Algorithmic
Concepts in Scientific FORTRAN Programs
J. R. Hagemeister, S. Bhansali, and C. S. Raghavendra
Washington State University, Pullman

Run-Time Versus Compile-Time Instruction Scheduling in Superscalar (RISC)
Processors: Performance and Tradeoffs
Allen Leung, Krishna V. Palem, and Cristian Ungureanu
New York University, New York

Two-Dimensional Orthogonal Tiling: From Theory to Practice
R. Andonov, H. Bourzoufi, and Sanjay Rajopadhye
Campus Universitaire de Beaulieu, France


                               2:00PM-4:00PM
                                Session IV-A

                        Image and Signal Processing
                           Chair: J. Mohan Kumar
                      Curtin University of Technology
                                 Australia

A New Efficient Edge Extraction Algorithm for Images Using Directional
Tracing Techniques
S. S. Iyengar, Y. Wu, and Hla Min
Louisiana State University, Baton Rouge

An Efficient Encoding Algorithm for Image Compression Hardware Based on
Cellular Automata
S. Bhattacharjee, U. Raghavendra, D. Roy Chowdhury, and P. Pal Chaudhuri
Indian Institute of Technology, Kharagpur

A Comparison of Bit-Serial and Multi-bit Processor Element in Real-Time
Signal Processing SIMD Architecture
Anders Astrom, Michael Hall, and Anders Edman
Linkoping University, Sweden

A Parallel Algorithm for Stereo Vision Based on Correlation
J. C. M. van Beek and J. J. Lukkien
Eindhoven University of Technology, The Netherlands

Spatial Frequency Based Motion Estimation for Image Sequence Compression
Vinod Menezes, S. K. Nandy, and Biswadip Mitra
Texas Instruments (India) Ltd, Bangalore

Load Balancing Strategies for Symbolic Vision Computations
Yongwha Chung, Jongwook Woo, Ramakant Nevatia and Viktor K. Prasanna
University of Southern California, Los Angeles


                               2:00PM-4:00PM
                                Session IV-B

                            Distributed Systems
                             Chair: Swarn Kumar
                             Boeing Corporation

Fault Tolerant Networks of Workstations
John Morris and Neil LeFevre
University of Tasmania, Australia

A Protocol for Lossy Transmission of Digital Video
Sundeep Oberoi
Applied Technology Group, Bombay

Independent Node and Process Recovery in Message Passing Distributed Systems
Subhash Bhalla and M. V. Sreenivas
The University of Aizu, Japan

A New Study for Fault-Tolerant Real-Time Dynamic Scheduling Algorithms
G. Manimaran and C. Siva Ram Murthy
Indian Institute of Technology, Madras

A Single Phase Protocol for the Total and Causal Ordering of Group
Operations in Distributed Systems
Chengzheng Sun and Piyush Maheshwari
Griffith University, Australia

Incorporating Fault Tolerance in Superscalar Processors
Manoj Franklin
Clemson University, Clemson

Analysis of Piggybacked Token-Passing MAC Protocol with Variable Buffer Size
for WDM Star-Coupled Photonic Network
Ashwani K. Ramani and Selvakennedy S.
University of Pertanian, Malaysia


                               2:00PM-4:00PM
                        Industrial Track Session II
                                    TBA

                               4:30PM-6:30PM
                                   Panel

 "Supercomputers as a commodity: Can scientific and commercial computing be
                      performed on the same machine?"

Moderator: Arvind, MIT

Panelists:
Vijay P. Bhatkar, C-DAC
Rajiv Gupta, HP Labs
Kei Hiraki, University of Tokyo
Chris Jesshope, Masey University
Rishiyur S. Nikhil, DEC CRL
Greg Papadopoulos, SUN Microsystems
N. Radhakrishnan, US ARMY CEWES
Marc Snir, IBM T. J. Watson Research Centre

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                           SATURDAY, DECEMBER 21

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                               9:00AM-10:00AM
                              Keynote Address

     "Efficient Access and Delivery of Images for the Digital Library"
                                Oscar Ibarra
                  University of California, Santa Barbara


                              10:30AM-12:30PM
                                Session V-A

                                 Algorithms
                            Chair: Bhabani Sinha
                        Indian Statistical Institute
                                  Calcutta

Efficient Parallel Prefix Algorithms on Fully Connected Message-Passing
Computers
Yen-Chun Lin and C. M. Lin
National Taiwan Institute of Technology, Taiwan

Multicast Communication Algorithm on a Wormhole-Routed Star Graph
Interconnection Network
Jelena Misic
Hong Kong University of Science and Technology

Implementing String-to-String Correction and Longest Common Subsequence
Problems on the Sequent Symmetry Multiprocessor
Sajal K. Das, Ajoy K. Datta, and Surendra Pothuru
University of North Texas, Denton, and University of Nevada, Las Vegas

A Parallel Test Generation for Combinational Circuits Based on Boolean
Satisfiability
Yuzhong Sun and Daozheng Wei
Institute of Computing Technology, P.R.C.

Parallel Algorithm for Maximum Empty L-Shaped Polygon
A. J. Preetham, Kamala Krithivasan, C. Pandu Rangan, and Jop F. Sibeyn
Indian Institute of Technology, Madras

Multithreading Implementation of a Distributed Shortest Path Algorithm on
EARTH Multiprocessor
Parimala Thulasiraman, Xin-Min Tian, and Guang R. Gao
McGill University, Montreal


                              10:30AM-12:30PM
                                Session V-B

                                Architecture
                            Chair: D. Jayasimha
                          Intel Corp., Santa Clara

A Multithreaded Architecture for the Efficient Execution of Vector
Computations within a Loop Using Status Field
Sung Dae Youn and Ki Dong Chung
Pusan National University of Technology, Republic of Korea

Performance Evaluation of a RISC Neuro-Processor for Neural Networks
Suthikshn Kumar, Kevin Forward, and M. Palaniswami
The University of Melbourne, Australia

Order-Configurable Programmable Power-Efficient FIR Filters
Chong Xu, Ching-Yi Wang, and Keshab K. Parhi
University of Minnesota

Quantitive Studies of Data Locality Sensitivity on the EARTH Multithreaded
Architecture: Preliminary Results
Xin-Min Tian, Shashank Nemawarket, Guang R. Gao, Herbert Hum, Olivier
Maquelin, Kevin Theobald, and Angela Sodan
McGill University, Montreal

A Distributed Barrier Synchronization Solution in Hardware for 2D-Mesh
Multicomputers
Martha Ximena Torres Delgado, and Sergio Takeo Kofuji
Universidade de Sao Paulo, Brazil

Connection Caching Technique with Host Grouping
Soomi Yang and Yookun Cho
Seoul National University, Republic of Korea

A Linear Systolic Algorithm and Architecture for Convex Bipartite Matching
N. Ranganathan and Rajesh Chandra
University of South Florida


                               1:30PM-3:30PM
                                Session VI-A

                     Scheduling and Resource Allocation
                           Chair: R. Shyamasundar
                                    TIFR

Evaluation of Static Scheduling Algorithms Improved with Partial Strict
Triggering of Program Graph Nodes
Milan Ojstersek, Viljem Zumer, Ljubo Pipan, Aleksander Kvas, and Boris Benko
University of Maribor University of Ljubljana, Slovenia

On-line Scheduling of Hard Real-Time Tasks on Multiprocessors
M. Dominic and Bijendra N. Jain
Indian Institute of Technology, Delhi

Path-Based Computing: A New Paradigm for High Performance Embedded Systems
Binoy Ravindran and Lonnie R. Welch
New Jersey Institute of Technology, Newark

A Robust and Flexible Microeconomic Scheduler for Parallel Computers
Ion Stoica and Alex Pothen
Old Dominion University, Norfolk

Dynamic Off-Line Scheduling for Multiscalar Processors
Vamsee K. Madavarapu and Manoj Franklin
Clemson University, Clemson

Buffer Allocation in Regular Dataflow Networks: An Approach based on
Coloring Circular-Arc Graphs
R. Govindarajan and S. Rengarajan
Indian Institute of Science, Bangalore

Adaptive resource allocation for embedded parallel applications.
Rajesh Jha and Mustafa Muhammad
Honeywell Technology Centre, Minneapolis
Sudhakar Yalamanchili, Karsten Schwan, Daniela Ivan-Rosu, and Chris deCastro
Georgia Institute of Technology


                               1:30PM-3:30PM
                                Session VI-B

                            Parallel Programming
                          Chair: Astrid Watermann
                           Research Center Julich

Communicating Data-Parallel Tasks: An MPI Library for HPF
Ian T. Foster,
Argonne National Labs
David R. Kohr, Jr., Rakesh Krishnaiyer, and Alok Choudhary
Syracuse University

Cidre: Programming with Distributed Shared Arrays
F. Andre, Y. Maheo, and Y. Dodard
Campus Universitaire de Beaulieu, France

PMDOS: A Testbed for Distributed and Parallel Algorithms Utilizing Idle
Machines in a Network
K. Prabhakar and G. Mohan
Centre for Development of Advanced Computing, Bangalore and Regional
Engineering College, Tiruchirappalli

PARDISC: A Cost Effective Model for Parallel and Distributed Computing
Achutha Raman R, Rajkumar, Hari Prakash G, and Bala Kishore B.
Centre for Development of Advanced Computing, Bangalore

A Co-operative Application Management Platform Based on Shared Virtual
Memory
Herve Guyennet and Jean-Christophe Lapayre
UFR Sciences et Techniques, France

An MPI Implementation of the BLACS
Vaibhav Deshpande and William Sawyer
Swiss Centre for Scientific Computing-ETH, Switzerland

A DSM-Based Structural Programming Environment for Distributed and Parallel
Processing
Lionel Brunie and Laurent Lefevre
Ecole Normale Superieure de Lyon, France



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                            SUNDAY, DECEMBER 22

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                                 Tutorial 1
                              8:30AM-12:00NOON

                       Mobile and Wireless Computing

                              Prathima Agrawal
                       Lucent Technologies Bell Labs

Who Should Attend: The intended audience is researchers as well as
practicing engineers interested in recent developments and design issues in
the above topic. The tutorial is suited to both computing and communication
professionals. In addition, service providers (PCS, cellular, Internet, for
example), as well as computing and communication equipment developers will
find value in the tutorial contents.

Course Description: The tutorial is on the architecture and networking
technology, and design techniques, underlying mobile multimedia computing
systems. We shall first present the current state of the art, and introduce
various core concepts including wireless access, mobility management, and
location management in existing cellular voice and mobile IP systems. Next,
we shall focus on the emerging mobile multimedia networked computing
systems. We shall describe research issues in (i) multimedia-oriented
network infrastructure capable of supporting mobility and wireless access,
and (ii) portable wireless terminals for mobile multimedia access. The
tutorial shall present approaches to problems such as providing end-to-end
quality of service (latency, synchronization) for mobile multimedia
applications. The tutorial will end with a presentation of application level
issues such as adaptation to mobility events, and the performance and energy
efficiency impact of the terminal-network computation partitioning.
Throughout the tutorial, we shall use the SWAN (SeamlessWireless ATM
Network) system from Bell Labs and other research systems elsewhere as
examples.

Lecturer: Prathima Agrawal heads the Networked Computing Research Department
at Lucent (formerly AT&T) Bell Laboratories in Murray Hill, NJ. She received
her BE and ME degrees in Electrical Communication Engineering from the
Indian Institute of Science, Bangalore, India, and a Ph.D. degree in
Electrical and Computer Engineering from the University of Southern
California. Her research interests are computer networks, mobile computing,
multimedia, parallel processing architectures, and VLSI CAD. She has over
120 technical publications and holds 8 US patents. She is a Fellow of the
IEEE.

                                 Tutorial 2
                              8:30AM-12:00NOON

                  Scalable Parallel Computer Architectures

                               Chris Jesshope
                       Masey University, New Zealand

Who Should Attend: Students or practicing engineers with an interest in
computer architecture who wish to know what the real issues are in making
parallel computers truely scalable or who may be mystified by the range of
approaches adopted to achieve this goal by commercial computer manufac-
turers. A basic understanding of computer architecture will be assumed,
although the lack of this would not be a barrier to the interested student.

Course Description: The objective of this tutorial is the understanding of
the principles of building scalable distributed memory parallel computers.
This involves software models as well as detailed architectural solutions.
It will focus on the principal issues and thus, be independent of any one
manufacturer's approach. It will be shown that the major principal issue is
the high latency access to data and consequently we will show the need for
reducing the latencies and also tolerating any remaining latency. The former
is largely an issue of network design, while the latter includes such
techniques as caching, prefetch and buffer and asynchronously scheduled
microprocessors. These various architectural methods for tolerating latency
will be studied and compared.
No such course would be complete without considering the programming issues
and so these will also be considered. Issues such as how high level programs
may be translated into the appropriate code and distributed control
structures will be discussed.

Lecturer: Professor Jesshope is a prominent researcher in the field of
parallel computer architecture and was the author of one of the first books
published in this subject. He has spent over 20 years in this field both
first as a programmer and later as a computer architect. He has published
many books, reports and papers in this area and has been invited to give
presentations on his experience at international conferences in over 15
countries throughout the world. He is currently Racal professor of IT at the
University of Surrey in the UK but will be taking up a new appointment as
head of department in Computer Science at Massey University in New Zealand
in September of this year. He is currently Honorary Editor of the IEE
Proceedings Computer and Digital techniques and is Steering Committee
Chairman for the EuroPar Conference series.

                                 Tutorial 3
                              8:30AM-12:00NOON

                    Object Oriented Parallel Programming

                             Laxmikant V. Kale
                 University of Illinois at Urbana-Champaign

Who Should Attend: This broad-based tutorial is intended for anyone
interested in parallel programming, including researchers who wish to
understand the issues in parallel object oriented programming, application
programmers interested in using it, and managers who wish to keep abreast of
the new technologies. Prerequisites: rudimentary knowledge of parallel
computing, and possibly of C++ will be helpful.

Course Description: Can object- oriented techniques help control the
substantial complexity of parallel programming? This question has generated
significant research efforts over the past several years. The tutorial
provides an overview of these research efforts and the resultant languages
and systems. It emphasizes the issues involved in designing parallel
object-based languages and the techniques involved in using them effectively
in real-world applications. After introducing the basic ideas and
motivations, the tutorial will focus on specific issues involved in the
design, implementation, and utility of parallel object-based languages. It
will also present several specific languages (including Charm++, PC++, CC++,
ABC++, UC++), in an issue-centered manner. The issues examined include
language primitives, object mapping, dynamic load balancing, concurrency,
interaction of objects with threads, flow of control, support for
data-parallel and irregular applications, compilation issues, application
experience, and future issues such as relationship with CORBA and Java.

Lecturer: Laxmikant V. Kale is an Associate Professor of Computer Science at
the University of Illinois, where he leads the Parallel Programming
Laboratory. He is an active researcher in the area of parallel object-based
programming, with emphasis on message-driven execution. He led the
development of the Charm++, which is a pragmatic system, supported by
powerful tools, and used for several real-world applications. In addition,
his current research interests include irregular parallel computations,
prioritization and load-balancing, automated performance analysis,
multi-lingual interoperabilty and runtime systems, parallel discrete event
simulations, and applications in computational biology and operations
research.

                                 Tutorial 4
                               1:30PM-5:00PM

High Performance Simulation: Possibilities and Pitfalls in Decomposition and
                                  Mapping

                                P.M.A. Sloot
                          University of Amsterdam

Who Should Attend: Computer scientists, engineers, scientists from the
natural sciences, interested in large scale simulations. Anyone interested
in practical advice in modelling for parallel simulation.

Course Description: This tutorial gives an introduction to the current state
of High Performance Simulation with emphasis on practical aspects of domain
decomposition and load balancing.

Part I:
Introduction to Domain decomposition and cost functions Mapping strategies

Part II:
Decomposition Methods:
Scattered Decomposition
Simulated Annealing
Genetic Algorithms

Part III:
Bisection Methods:
Recursive Coordinate, Graph and Orthogonal Bisection
Recursive Spectral Bisection

Part IV:
Load balancing for MPP versus Workstation Clusters

Examples from Engineering, Chemistry and Biology will be discussed.

Lecturer: Peter M.A. Sloot is an associate professor in parallel and
scientific computing and simulation at the University of Amsterdam. He has
written and managed a large number of externally funded simulation projects.
In 1990 he founded the interdisciplinary working group on Parallel
Scientific Computing and Simulation. In 1993 he co-founded the facilitair
centre for complex computer systems (IC3A). In 1996 he founded the
interuniversity Institute for Computational Science (ICS). He has published
over 120 papers on various theoretical and experimental topics in the field
of computational science. He has been in the organizing committees of a
large number of national and international conferences and workshops on
scientific computing. His current research interest is in the modelling and
implementation of dynamic complex systems for parallel simulation.
His teaching experience and interest is in: Architecture and Parallel
Computing (for undergraduate computer scientists) Numerical Physics (for
undergraduate physicists) Modeling and Simulation (for undergraduate
mathematicians) Advanced Modeling and Simulation (for various Post graduate
Summer Schools) Parallel Scientific Computing and Simulation (for Post
graduate and PhD).

                                 Tutorial 5
                               1:30PM-5:00PM

         Recent Advances in Concurrent Object Oriented Programming

                                Gul A. Agha
                           University of Illinois

Who Should Attend: No prior knowledge of issues in parallel computation or
object-oriented programming will be assumed. The course should be useful to
those interested in tracking developments in new parallel processing
technologies and providing distributed software development. It is also
recommended for technical personnel who want to learn about the feasibility
and utility of rapidly increasing computational power provided by emerging
technological tools.

Course Description: The course will cover recent developments in Concurrent
Object Oriented Programming and their use in large-scale parallel
computation. We will discuss proposed languages and architectures to build
and efficiently utilize scalable parallel computers. A number of models of
concurrent and distributed computing will be discussed; the actors model of
concurrent computation will be specifically described in detail. Techniques
for runtime support and compilation of concurrent languages will be
discussed including issues such as naming, reflection, location
transparency, and mobility. The current state of visual programming,
dependability, language abstractions and program reasoning tools will be
surveyed.

Lecturer: Professor Gul A. Agha is Director of the Open Systems Laboratory
at the University of Illinois at Urbana-Champaign. His widely cited book,
Actors: A Model of Concurrent Computing in Distributed Systems, (MIT Press,
1986) provided a basis for a number of research projects in concurrent
program ming. Dr. Agha is the Editor-in-Chief of IEEE Parallel and
Distributed Technology. He is Associate Editor of the journals ACM Computing
Surveys and Theory and Practice of Object Systems. Dr. Agha is an ACM
International Lecturer, a past recipient of the Incentives for Excellence
Award from Digital Equipment Corporation, and the Naval Young Investigator
Award from the US Office of Naval Research. He was named a fellow in the
University of Illinois Center for Advanced Study in 1992. Dr. Agha has given
invited talks at over 10 international conferences in the past five years,
published papers in a number of areas related to distributed systems,
including programming languages, fault-tolerance, real-time systems,
mathematical foundations of concurrent programming, parallel algorithms and
visual programming.

                                 Tutorial 6
                               1:30PM-5:00PM

                    Why Systolic Arrays: the Real Answer

                        P. Quinton and S. Rajopadhye
                               IRISA, France

Who Should Attend: This tutorial is intended for researchers interested in
the interplay between parallel architecture (regular arrays), programming
languages (functional data parallel), and compilation (loop
parallelization). It describes program analysis and transformation
techniques for developing (software, hardware or hybrid) solutions to
applications in telecommunications, signal and image processing, medical
imaging, etc.

Course Description: Seventeen years after Kung and Leiserson gave massive
parallelism a catchy name, what have we learnt from systolic arrays?
This tutorial describes a key contribution of the research on systolic array
synthesis: the "polyhedral model". It provides a unified framework for
reasoning about massively parallel, regular (not just nearest neighbor)
computations. Its influence goes beyond its original scope, which is itself
seeing a resurgence, given the recent trends in FPGAs and programmable
logic devices.
The course introduces the foundations of the model, and discusses its impact
on loop parallelization, data parallel functional languages and program
transformation methods. It includes simple exercises to reinforce the ideas,
and will be accompanied by a demonstration of the Alpha language(a
functional data parallel language based on the polyhedral model) and
transformation system (prototype tools for implementing Alpha programs,
either as dedicated VLSI, or as sequential or parallel programs) currently
being developed at IRISA.

Lecturers: Patrice Quinton (Diplome d'Ingenieur, 1972, Doctorat d'etat 1981)
heads the group on parallel VLSI research at IRISA, Rennes. He works on
VLSI, parallel architecture and algorithms, and synthesis of regular arrays.
He is one of the pioneers of automatic systolic synthesis, and was the first
to make use of Karp Miller and Winograds' seminal results on Uniform
Recurrences. He was awarded the second prize of the Seymour Cray France
contest in 1986 for this research.
Sanjay Rajopadhye (B. Tech, 1980, PhD 1986) is a senior CNRS researcher at
IRISA, Rennes. His research deals with mapping regular parallel computations
to parallel architectures, paticularly systolic array synthesis. He is also
interested in VLSI, functional programming and asynchronous circuits. His
doctoral dissertation contributed to the foundations of the polyhedral
model. He received the best paper award at ASAP 1995 and the best
presentation award at Parcella 1994.


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                             LOCAL INFORMATION

---------------------------------------------------------------------------

The conference will be held at Technopark. Technopark campus is located
adjacent to the University of Kerala. It is approximately 25 minutes by a
taxi-ride from the airport and is approximately 45 minutes from the Kovalam
beach area. Technopark numbers are: Tel: +91-471-417222 and Fax:
+91-471-417971.

About Trivandrum:
Trivandrum (Thiruvananthapuram, the City of the Endless Serpent) is located
near the southern-most tip of India. It is the capital of the state of
Kerala. With its golden beaches and emerald green palm trees, it is a
popular tourist destination. Trivandrum is home to some leading scientific
and technological institutions in India including the Vikram Sarabhai Space
Centre, and the Centre for Earth Science Studies. The city has a number of
tourist attractions. Places of tourist attraction include Raja Ravi Varma's
dramatic paintings at the Chitra Art Gallery, buildings from colonial times
which combine indigenous architectural styles with European ones, the Napier
museum with a fine collection of bronzes, and the Oriental manuscript
library which preserves ancient palm leaf manuscripts. Further information
on Trivandrum can be found through the Web at the URLs, http://www.cs.cmu.
edu/afs/cs/user/vipin/www/kerala.html and
http://www.granada.com/kerala/map/.

Visa and Passport:
All participants who are not citizens of India must obtain a valid visa from
Indian Consulates or High Commissions. The procedure may take some time,
consult with your travel agent in advance.

Currency:
The currency is the Indian Rupee. The conversion rate at the time of this
publication is 1 US $ to Rs. 35.00. Credit cards are accepted in most luxury
hotels but not in most commercial establishments. The Reserve Bank of India
may have certain restrictions on converting Rupees to other currencies. For
details, check with an Indian Consulate or your travel consultant.

Time and Weather:
The Indian Standard Time (IST) is 5 1/2 hours ahead of the Greenwich Mean
Time (GMT) and is 13 1/2 hours ahead of the U. S. Pacific Standard Time
(PST). Trivandrum has a tropical weather. In late December, the minimum
recorded temperature is 23 degrees C (73 degrees F) and the maximum recorded
temperature is 32 degrees C (90 degrees F). Light clothing is recommended.

Travel:
Trivandrum has an international airport. It may also be convenient to fly in
from other major international airports such as Madras and Bombay. It is
advisable to make travel plans (including airline and hotel reservations) as
early as possible since travel to and from India is very heavy during the
months of December and January. The meeting does not endorse any travel
agency, however, to assist international travelers with late airline
reservations a block of seats has been reserved. You may contact Globalink
Travels in the Los Angeles area at +1 818-972-9525 for details.

Accommodation:
The Kovalam Ashok Beach Resort is offering a special rate of US $ 162 (per
night, single) US $ 198 (per night, double) for meeting participants. The
rate includes all taxes. The resort is a deluxe five star hotel. It is less
than 45 minutes by a taxi-ride from Technopark. The airport is approximately
30 minutes by a taxi-ride from the hotel. The cost of the ride to or from
the city can vary, and a one-way taxi-ride (in an air conditioned Ambassador
car) will cost around US $8 including tip.
To assist the participants, The Great India Tour Company Pvt. Limited has
reserved a block of rooms at the above resort. Details can be found in the
Hotel Reservation Form.
There are a number of alternate hotels in Trivandrum. However, the quality
of service can vary dramatically. Check with your travel consultant in
advance to ensure a comfortable stay.


------------------------------------------------------------------------------------

                      HiPC '96 ADVANCE REGISTRATION FORM

------------------------------------------------------------------------------------

PLEASE PRINT:

Name: _________________________________________________________________________
		Last/Family          		First         		 M.I.                   

Name on Badge ______________________________________

Affiliation: ____________________________________________________________________

Address/MailStop:________________________________________________________________

City/State/Zip/Country: _________________________________________________________

Phone (day time):________________________ Fax:___________________________________

IEEE Membership Number:___________________E-Mail:________________________________

Dietary needs:________  Vegetarian  ________ Spicy

PLEASE  CIRCLE  APPROPRIATE  FEES:
Conference Registration Fees:   IEEE-Member   	Non-Member    	Student
			        US$/Rs.      	US$/Rs.      	US$/Rs.
Advance Registration            250/8750      	300/10500      	250/8750
(until November 15, 1996)

On-site Registration     	300/10500     	350/12250     	300/10500

The registration fee includes a copy of the  proceedings, lunches, and
refreshments on December 19, 20, and 21 and conference banquet and Reception.
Conference registration fee does not include participation in the tutorials.
Tutorials are open to conference registrants only.

Tutorial Registration Fees:     IEEE-Member  	Non-Member  	Full-time Student
(Per tutorial)			US$/Rs.      	US$/Rs.     	US$/Rs.

Advance Registration            50/1750    	75/2500 	50/1750
(until November 15, 1996)

On-site Registration       	75/2500		100/3500     	75/2500

The tutorial registration fee includes participation in the tutorial, 
a copy of the tutorial notes and refreshments.
	Tutorial 1  ___		 Tutorial 2  ___		Tutorial 3  ___
	Tutorial 4  ___		 Tutorial 5  ___       		Tutorial 6  ___

			Conference Registration Fee: ________
			Tutorial Registration Fee: __________
			Total Amount Enclosed: ______________

Payment must be enclosed. Please make cheques payable to International Conference on 
High Performance Computing. All cheques MUST be either in U.S. Dollars drawn on a
U.S. Bank or in Indian Rs. drawn on an Indian bank.  Participants currently residing
in India may pay in Indian Rs., all others (including NRIs) must pay in U.S. Dollars.
Written requests for refunds must be received (by the appropriate Finance Co-Chair)
no later than Nov. 25, 1996. Refunds are subject to a US $50 (Rs. 1500) processing fee.
All no-show registrants will be billed in full. Registration after November 15, 1996 
will be accepted on-site only. Please do not send this registration form to the 
General Co-Chairs or to the Program Chair.
Please mail to:

HiPC '96						HiPC '96
c/o Ajay Gupta						c/o A. K. P. Nambiar
Computer Science Department                             C-DAC
Western Michigan University				2/1, Brunton Road
Kalamazoo, MI 49008, USA.				Bangalore, 560025, India
Email: hipc96@cs.wmich.edu   Fax: +1(616)387-3999       Email:nambiar@cdacb.ernet.in

Participants currently residing in India are requested to send their completed 
registration form to Mr. Nambiar, all others are requested to send it
to Professor Ajay Gupta.  Scholarships to a) full time students and b) faculty
at Indian academic institutions and to researchers at Indian government
establishments may be available from agencies within India.
For details contact  Mr. A K P Nambiar, C-DAC,
Bangalore(email: nambiar@cdacb.ernet.in). These scholarships are not available to 
participants from non-Indian institutions.

--------------------------------------------------------------------------

                    HiPC '96 HOTEL RESERVATION FORM
 
--------------------------------------------------------------------------
Travel to India during the month of December is usually very heavy. To
assist international travelers, the Great India Tour Company has
contacted several local hotels.

HOTEL(ALL RATES ARE IN US $)	     SGL/Night	   DBL/Night	

1) KOVALAM ASHOK BEACH RESORT (5 Star)	162	     198	
2)    SOUTH PARK (4 Star)			
              STANDARD ROOM	         54	      66	
              PARK CHAMBERS	         66	      78	
              DOUBLE SUITE	         96          108	
3)     MASCOT HOTEL (3 Star)			
              STANDARD ROOM	         30	      41	
              DELUXE ROOM			      74	
              DELUXE SUITE			      88	

The above rates are for room only and are inclusive of all applicable
taxes. The above rates are available from 18 December to 23
December. The cut-off date for reservation is 1 October
1996. Reservation requests received after 1 October cannot be
guaranteed. In addition to the room charge, the Great India Tour
Company will charge a service fee of US $10/room.

Please reserve accommodation for: 

FULL NAME_____________________________________________________________
ADDRESS_______________________________________________________________
______________________________________________________________________
TEL____________________________________	FAX___________________________
HOTEL PREFERRED:_______________________ TYPE OF ROOM__________________
NUMBER OF PERSONS:_____________________
CHECK IN DATE:_________________________	FLIGHT DETAILS:_______________
CHECK OUT DATE:________________________	FLIGHT DETAILS:_______________
NUMBER OF NIGHTS:______________________	(CHECK OUT TIME IS 12 NOON)

TOTAL AMOUNT ENCLOSED = (HOTEL RATE) x NO. OF NIGHTS + US $10 =_______
CASHIER'S CHECK/DEMAND DRAFT NO:___________________________
MAKE YOUR CHECK IN FAVOUR OF the GREAT INDIA TOUR COMPANY PVT
LTD. PAYABLE AT BANK OF BARODA, PALAYAM, TRIVANDRUM - 695 039 AND MAIL
THE COMPLETED FORM ALONG WITH YOUR CHECK TO:

MANOJ KURIAKOSE
HiPC '96
GREAT INDIA TOUR COMPANY PVT LTD.
MULLASSERY TOWERS, VANROSS JUNCTION
TRIVANDRUM - 695 039, INDIA
TEL: +91-(471) 331516/331585/331522/231422   FAX: +91-(471) 330579

PLEASE NOTE THAT THE COMPLETED FORM ALONG WITH YOUR PAYMENT SHOULD
REACH THE ABOVE ADDRESS BEFORE 1 OCT. 1996.

REFUND POLICY:
CANCELLATION BEFORE 1 OCTOBER '96 - REFUND OF HOTEL ROOM CHARGES ONLY.
CANCELLATION ON OR BEFORE 18 NOVEMBER '96 - ONE NIGHT RETENTION CHARGE APPLIES.
CANCELLATION AFTER 18 NOVEMBER '96 - NO REFUND.
SERVICE FEE IS NON REFUNDABLE. ALL CANCELLATIONS MUST BE RECEIVED IN WRITING.
ALL CORRESPONDENCE REGARDING ACCOMODATION SHOULD BE SENT TO THE ABOVE ADDRESS.





