Newsgroups: comp.arch,comp.parallel.pvm,comp.parallel.mpi,comp.org.acm,comp.org.ieee,comp.sys.super
From: djayasim@magnus.acs.ohio-state.edu (D N Jayasimha)
Subject: ADVANCE PROGRAM - Int'l Parallel Processing Symposium IPPS '96
Organization: The Ohio State University
Date: 21 Jan 1996 00:08:16 GMT
Message-ID: <4ds05g$fp0@charm.magnus.acs.ohio-state.edu>


        (Note: Includes Registration Form and Hotel Reservation info.)

          IPPS '96 - 10th INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM

                               APRIL 15-19, 1996
                      SHERATON WAIKIKI, HONOLULU, HAWAII

                                  Sponsored by
                            IEEE Computer Society 
                   Technical Committee on Parallel Processing
                        In cooperation with ACM SIGARCH

                                ADVANCE PROGRAM

-------------------------------------------------------------------------------

For easier reading, ask for a hard copy of this advance program.
Contact:
        Regina Morton,
        Department of EE-Systems, EEB 200,
        3740 McClintock Avenue,
        University of Southern California,
        Los Angeles, CA 90089-2562

        email: morton@pollux.usc.edu
        Fax: (213) 740-4418

Additional information regarding IPPS '96 events may be obtained at

http://www.usc.edu/dept/ceng/prasanna/home.html or

contact IPPS '96 General Chair V.K. Prasanna (prasanna@ganges.usc.edu ).

-------------------------------------------------------------------------------


                                    CONTENTS

   * IPPS '96 PROGRAM

   * SYMPOSIUM ORGANIZATION 

        o MONDAY, APRIL 15
          Registration
          Workshops 1-5

        o TUESDAY, APRIL 16
          Registration
          Workshops 6-10
          Tutorials 1 and 2

        o WEDNESDAY, APRIL 17
          Registration
          Keynote Address
          Technical Sessions 1-9

        o THURSDAY, APRIL 18
          Registration
          Keynote Address
          Technical Sessions 10-15
          Industrial Track Sessions
          Panel Session

        o FRIDAY, APRIL 19
          Registration
          Keynote Address
          Technical Sessions 16-21
          Beach Party !!!!!!

   * LOCATION

   * SYMPOSIUM REGISTRATION FORM

   * HOTEL RESERVATION FORM


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                                    PROGRAM

IPPS '96 PROGRAM SCHEDULE

IPPS '96 will include the customary events of contributed technical papers,
keynote addresses, workshops, and tutorials. An industrial track has been
organized and some commercial participants will mount exhibits. The workshops
will be conducted on Monday & Tuesday only and the tutorials will be presented
on Tuesday. Wednesday through Friday will feature sessions for contributed
papers along with industrial track presentations and a panel discussion on
Thursday. Each day will open with a keynote address.

CONTRIBUTED PAPERS

There will be 126 contributed technical papers to be presented in 21 technical
sessions. Topics span the design, development, use, and analysis of parallel
processing systems.

KEYNOTE ADDRESSES

Wednesday, April 17th: Can Multithreaded Programming Save Massively Parallel
Computing?
Charles E. Leiserson, Massachusetts Institute of Technology
Thursday, April 18th: MPPs versus Clusters
Charles L. Seitz, Myricom, Inc.
Friday, April 19th: Clusters for Commercial Computing: An Invisible
Architecture
Gregory F. Pfister, IBM Server Group, Austin

PANEL

Thursday, April 18th:
For a Massive Number of Massively Parallel Machines: What Are the Target
Applications, Who Are the Target Users, and What New R&D Is Needed to Hit the
Target???
Moderator: H.J. Siegel, Purdue University

WORKSHOPS

Ten workshops have been organized: five begin on Monday, five on Tuesday and
all conclude by the end of Tuesday. Workshops are open to all symposium
registrants, and descriptions of each follow here in the Advance Program. Since
submission criteria and deadlines vary, contact individual workshop organizers
for more information. IPPS '96 workshops are:

(Starting on Monday, April 15th)

1. Formal Methods for Parallel Programming: Theory and Applications
2. Reconfigurable Architectures and Algorithms
3. Fault-Tolerant Parallel and Distributed Systems
4. Parallel and Distributed Real-Time Systems
5. Heterogeneous Computing

(Starting on Tuesday, April 16th)

6. Job Scheduling Strategies for Parallel Processing
7. High-Level Programming Models and Supportive Environments
8. Randomized Parallel Computing
9. Solving Irregular Problems on Distributed Memory Machines
10. High-Speed Network Computing

TUTORIALS

There will be two tutorials, and both will be held on Tuesday. Tutorial 1 will
be held in the morning and Tutorial 2 will be held in the afternoon, so it will
be possible to register for both sessions. The topics are:

1. An Introduction to the Message-Passing Interface (MPI)
2. Introduction to Parallel and Distributed Simulation Techniques With
   Applications to VLSI, Multiprocessor Architectures, and Mobile
   Telecommunication Systems

INDUSTRIAL-COMMERCIAL TRACK

The Industrial Track on Thursday will consist of technical papers authored by
representatives from commercial vendors some of whom will also be exhibiting.
For more information on participation and planned exhibits, contact
Industrial-Commercial Chair John K. Antonio (antonio@cs.ttu.edu).

SOCIAL EVENTS

Refreshments will be served at several breaks throughout the day. On Wednesday
and Thursday, there will be a 3 hour mid-day break, and IPPS attendees are
encouraged to organize recreational and explorational activities during this
time. It will also be a chance to "hit the beach" and return refreshed for late
afternoon sessions. An IPPS get-together is planned for Wednesday evening
(details at registration) and everyone is invited to the traditional Beach
Party on Friday.

REGISTRATION

Note that advance registration must be sent to the IEEE Computer Society by March 15, 1996. Registrations after March 29, 1996 will be accepted on-site only.


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                                  ORGANIZATION

SYMPOSIUM CHAIR

Viktor K. Prasanna,
University of Southern California

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PROGRAM CHAIR

Kai Hwang,
University of Hong Kong &
University of Southern California

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PROGRAM VICE-CHAIRS

Algorithms: Mikhail Atallah, Purdue University
Applications: John Gustafson, Ames Laboratory
Architecture: Jean-Loup Baer, University of Washington
Software: Gul Agha, University of Illinois, Urbana

INDUSTRIAL-COMMERCIAL CHAIR
John K. Antonio, Texas Tech University

TUTORIALS CHAIR
Sajal Das, University of North Texas

FINANCE CHAIR
Bill Pitts, Toshiba America Information Systems, Inc.

LOCAL ARRANGEMENTS CHAIR
Susamma Barua, California State University, Fullerton

PUBLICITY CHAIR
Sally Jelinek, Electronic Design Associates

PUBLICITY COORDINATORS
Europe-Africa-Middle East: Jose Rolim, University of Geneva
Pacific Rim: Piyush Maheshwari, Griffith University, Australia
North America: D.N. Jayasimha, Ohio State University
East Asia: Mikhail Mahaniok, Academy of Sciences of Belarus
Central/South America: Liria Matsumoto Sato, University of Sao Paulo, Brazil

PROGRAM COMMITTEE
Hussein Alnuweiri, University of British Columbia, Canada
Richard Anderson, University of Washington
Prith Banerjee, University of Illinois, Urbana
Thomas Bemmerl, RWTH Aachen, Germany
Francine Berman, University of California, San Diego
Laxmi Bhuyan, Texas A&M University
Thomas Casavant, University of Iowa
Danny Chen, University of Notre Dame
Andrew Chien, University of Illinois, Urbana
Francis Chin, Hong Kong University
Alok Choudhary, Syracuse University
Robert Cypher, Johns Hopkins University
Jack Dongarra, Oak Ridge National Laboratory
David Du, University of Minnesota
Michel Dubois, University of Southern California
Ian Foster, Argonne National Laboratory
Phillip Gibbons, AT&T Bell Laboratory
Ronald Greenberg, University of Maryland
Matthew Haines, NASA Langley Research Center
Oscar Ibarra, University of California, Santa Barbara
Joseph JaJa, University of Maryland
Ken Kennedy, Rice University
Vipin Kumar, University of Minnesota
Guo-Jie Li, Chinese Academy of Sciences
Kai Li, Princeton University
D. Martinez, MIT Lincoln Laboratory
Louise Moser, University of California, Santa Barbara
Lionel Ni, Michigan State University
David Padua, University of Illinois, Urbana
D.K. Panda, Ohio State University
Gregory Plaxton, University of Texas at Austin
Umakishore Ramachandran, Georgia Institute of Technology
C.P. Ravikumar, Indian Institute of Technology, Delhi
Rafael Saavedra, University of Southern California
Sartaj Sahni, University of Florida
Assaf Schuster, Technion, Israel
Kang Shin, University of Michigan
Behrooz Shirazi, University of Texas at Arlington
H.J. Siegel, Purdue University
David Wood, University of Wisconsin
Pen Yew, University of Minnesota
C.K. Yuen, National University of Singapore

STEERING COMMITTEE CHAIR
George Westrom, Odetics, Inc.

STEERING COMMITTEE
Larry Canter, CSA
K. Mani Chandy, Caltech
F. Tom Leighton, MIT
Viktor K. Prasanna, USC
George Westrom, Odetics, Inc.

SYMPOSIUM ADVISORY COMMITTEE
Anant Agarwal, Massachusetts Institute of Technology
Michel Cosnard, Ecole Normale Superieure de Lyon, France
Michael J. Flynn, Stanford University
Richard Karp, University of California, Berkeley
Gary Miller, Carnegie Mellon University
Ahmed Sameh, University of Minnesota
Charles L. Seitz, Myricom, Inc.
Leslie Valiant, Harvard University
Zeke Zalcstein, National Science Foundation

CHAIRMAN EMERITUS
Larry Canter, Computer Systems Approach, Inc.

SPONSORSHIP
The 10th International Parallel Processing Symposium is sponsored by the IEEE
Computer Society Technical Committee on Parallel Processing (TCPP) and is held
in cooperation with the ACM Special Interest Group on Computer Architecture
(SIGARCH). The support and participation of the following companies is
gratefully acknowledged:

Cambridge Parallel Processing
Center for Development of Advanced Computing
Cray Research Inc.
Electronics and Telecommunications Research Institute
IBM Systems/390 Division
Litton Guidance and Control Systems Inc.
Mercury Computer Systems Inc.
The Portland Group Inc.
Tandem Computers Inc.
Virtual Computer Corporation

IPPS '96 PROCEEDINGS
The 1996 proceedings will be published by the IEEE Computer Society Press and
made available to all registrants including students at the symposium. Extra
copies and proceedings from previous symposia may be obtained by contacting the
IEEE Computer Society.

WORKSHOP PROCEEDINGS
Proceedings from the workshops will vary in format and availability and cannot
be guaranteed to each IPPS registrant. However, a ticket for proceedings from
two workshops will be issued to each registrant. Printed copies will be
distributed at the beginning of each workshop with preference to those
participating in the workshop. This year, to help satisfy demand for workshop
proceedings, most will be available via the Web. Requests for additional
printed copies should be made to the individual workshop chair(s).

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                                MONDAY, APRIL 15

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Workshop 1

All Day Monday

1ST INTERNATIONAL WORKSHOP ON FORMAL METHODS FOR PARALLEL PROGRAMMING:
THEORY AND APPLICATIONS
Workshop Chair:
Dominique Mery
Institut Universitaire de France &
Universite Henri Poincare, France
-------------------------------------------------------------------------------

Program Committee:
Radhia Cousot, CNRS & Ecole Polytechnique, France
Pascal Gribomont, Liege, Belgium
Silvio Lemos Meira, Recife, Brazil
Dominique Mery (Chair), Nancy, France
Lawrence Paulson, Cambridge, UK
Xu Qiwen, Macau
Catalin Roman, St. Louis, USA
-------------------------------------------------------------------------------

Formal methods are widely investigated in academic institutions and, more
recently, used in industrial applications. By using mathematical notations,
systems and their properties are precisely described, and therefore formal
methods offer a way to achieve high level assurance of system quality. Formal
methods combine methodological aspects in a formal framework. Although they
appear to be difficult to apply, they are the only means of ensuring that an
implementation is correct with respect to a given specification. The
development of an algorithmic solution from a (formal) specification is carried
out with the help of mathematical techniques and tools.

The objective of the workshop is to gather together people, both from academia
and industry, who use and/or develop formal methods for parallel programming.
There are potentially many different approaches to improving the environment
for parallel programming. The (proof) tools and their user interface are
fundamental to formalisation of the parallel programming process.Papers have
been invited in areas such as (but are not limited to) the following:

- Methodological and theoretical aspects of parallel programming with respect
to the development of parallel programs: specification, verification,
refinement, compositionality, correctness, abstract interpretation,
transformation, translation, etc.
- Case studies developed with formal methods, particularly those with
industrial background
- Tools that support formal development of parallel programs, with emphasis on
re-use and modularisation
- Examples of existing formal languages (for example, RAISE, UNITY, B, VDM, Z,
SWARM, GAMMA, PVS, TLA, ISABELLE, etc.) and their application to parallel
program problems
- Comparative studies of existing formal methods for parallel programming

The workshop will include research papers as well as a panel discussion. There
will also be a session where participants can discuss work in progress.
Proceedings will be available at the symposium and via WWW.For more
information, please contact:

FMPPTA'96/Dominique Mery
Universite Henri Poincare-Nancy 1,
CRIN CNRS URA 262
Batiment LORIA, BP239
F-54506 Vandoe uvre-les-Nancy France
Vox: +33 83 59 20 14
Fax: +33 83 41 30 79
Internet: mery@loria.fr
WWW:http://www.loria.fr/~mery/fmppta96.html

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Workshop 2

All Day Monday

3RD WORKSHOP ON RECONFIGURABLE ARCHITECTURES AND ALGORITHMS
Workshop Co-Chairs:
Hossam ElGindy
University of Newcastle
Australia

Assaf Schuster
Technion
Israel
-------------------------------------------------------------------------------

Program Committee:
Peter Athanas, Virginia Polytechnic Institute
Fikret Ercal, University of Missouri-Rolla
Bradley Fawcett, Xilinx, Inc.
Russ Miller, SUNY-Buffalo
Stephan Olariu, Old Dominion University
Viktor K. Prasanna, USC
Sartaj Sahni, University of Florida
Heiko Schroeder, Univ. of Tech (Loughborough)
Arun Somani, University of Washington
Quentin Stout, University of Michigan
R. Vaidyanathan, Louisiana State Univerity
Charles Weems, University of Massachusetts

The 3rd Workshop on Reconfigurable Architectures and Algorithms will be held in
conjunction with IPPS '96. For the purpose of this workshop, a reconfigurable
architecture consists of processors connected by a reconfigurable network. The
topology of the network connecting the processors is fixed, whereas the
internal connections between the I/O ports of each processor can be configured
locally during execution of the algorithm. Numerous algorithms have been
presented in the scientific literature. They have addressed a wide range of
problems, e.g. computer vision, sorting, packet routing, embedding of fixed
topologies, and fault tolerance.
The workshop will feature keynote speakers, several sessions of submitted
research and position papers. A position paper presents a particular subject
which is in the center of interest for the community. Position papers may
include, but are not limited to the introduction and justification of a new
model or of a new line of research. The tradition of an informal panel
discussion and problem session, which was very fruitful in the previous
workshops, will continue.Proceedings will be available at the symposium and
later by public ftp.
Authors are invited to submit position papers and manuscripts which demonstrate
original research in all areas of reconfigurable architectures, algorithms, and
applications. The topics of interest include, but are not limited to :
Reconfiguration Networks, Custom Computing Machines, Complexity and
Scalability, Problem Solving Paradigms, Enabling Technologies, Mapping of fixed
topologies, and Algorithms (for graphics and animation, computer arithmetic,
image processing, computational geometry, and numerical problems).
All papers will be reviewed by the program committee. Send five (5) copies of a
complete paper or a detailed summary of a position talk to:
Assaf Schuster
Computer Science Department
Technion, Haifa
ISRAEL 32000

or (the preferred way), email 1 copy (plain postscript, NOT compressed, NOT
unencoded) to assaf@cs.technion.ac.il
Important Dates:
12 January 1996 (Manuscripts to be received)
16 February 1996 (Notification of decisions)
15 March 1996 (Final version due)

For further information, send e-mail to hossam@cs.newcastle.edu.au or
assaf@cs.technion.ac.il

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Workshop 3

All Day Monday

WORKSHOP ON FAULT-TOLERANT PARALLEL AND DISTRIBUTED SYSTEMS

Workshop Co-Chairs:
D.R. Avresky
Texas A&M University

D.R. Kaeli
Northeastern University
-------------------------------------------------------------------------------

Program Committee:
H. Arabia, University of Georgia
R. Booth, IBM Applications Solutions Division, Rochester
D. Bossen, IBM
J. Bruck, Caltech
B. Ciciani, University of Roma, Italy
B. Horst, Tandem
S. Hosseini, University of Wisconsin, Milwaukee
M. Karpovsky, Boston University
B. Lecussan, ONERA/CERT, France
D. Moldovan, SMU
S. Rangarajan, Northeastern University
M. Raynal, IRISA, France
K. So, AMD, Austin
K. Trivedi, Duke University
L. Young, Tandem

Increasingly large parallel computing systems provide unique challenges to the
researchers in dependable computing, especially because of the high failure
rates intrinsic to these systems. While commercial and scientific companies
share the need for massive throughput and low latency, dependability of service
is also a concern. In addition to providing uninterrupted service, commercial
systems must be free from data corruption. Achieving dependability in highly
scalable parallel and distributed systems poses a considerable challenge. As
the number of components increases, so does the probability of a component
failure. Therefore, improved fault tolerant technology is required for highly
scalable parallel and distributed systems.
The goal of this workshop is to provide a forum for researchers and
practitioners to discuss these and related issues of fault-tolerant parallel
and distributed systems. All aspects of design, theory and realization of
parallel and distributed systems are of interest.
Topics of interest include, but are not limited to:
- Fault-tolerant systems
- Fault-tolerant interconnection networks
- Reconfigurable fault-tolerant parallel and distributed systems
- Fault-tolerant parallel and distributed real-time systems
- Fault-tolerant parallel programming
- Scalable fault-tolerant architectures and algorithms
- Fault injection in parallel and distributed systems
- Dependability evaluation of fault-tolerant parallel and distributed systems

The workshop is sponsored by the IEEE Technical Committee on Parallel
Processing. For further information, please contact one of the following:
D.R. Avresky
Dept. of Computer Science
Texas A&M University
College Station, TX 77843-3112
Vox: (409) 862-4389
Fax: (409) 847-8578
Internet: avresky@cs.tamu.edu

D.R. Kaeli
Dept. of Electrical and Computer Engineering
Northeastern University
Boston, MA 02115
Vox: (617) 373-5413
Fax: (617) 373-8970
Internet: kaeli@ece.neu.edu

To submit papers, send six copies of a manuscript (at most 20 pages long
including figures and references) describing original unpublished research to
D.R Avresky by March 18 1996.

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Workshop 4

All Day Monday and Tuesday

4TH INTERNATIONAL WORKSHOP ON PARALLEL AND DISTRIBUTED REAL-TIME SYSTEMS
(WPDRTS)

Workshop Co-Chairs:
Dieter K. Hammer
Eindhoven University of Technology

Heonshik Shin
Seoul National University

Lonnie R. Welch,
Naval Surface Warfare Center
-------------------------------------------------------------------------------

The workshop will feature manuscripts that demonstrate original unpublished
research pertaining to real-time systems that are parallel and/or
distributed.The presentations will include systems that are experimental and
commercial systems, their scientific and commercial applications, and
theoretical foundations. Topics to be considered (as they relate to parallel
and distributed real-time systems) include:
- Fault tolerance
- Run-time systems
- Architecture and hardware
- Multimedia
- Communications and networking
- Real-time databases
- Analysis, validation, and simulation
- New paradigms and languages
- Formal methods
- Tools and environments
- Systems engineering and reengineering
- Embedded systems
- Real-time signal and image processing
- Benchmarking
- Software architectures
- Ada 95
-------------------------------------------------------------------------------

The workshop program will include a panel discussion on the topic "Benchmarking
for Real-Time High Performance Computing." If interested in participating as a
panelist, please send a position paper to the panel Chair:
Richard Games
The MITRE Corporation
rg@mitre.org.
-------------------------------------------------------------------------------

Program Chairs:
Dieter K. Hammer (Chair for Europe and Africa)
Eindhoven Univ. of Technology
Internet: hammer@win.tue.nl

Heonshik Shin (Chair for the Pacific Rim)
Seoul National University
Internet: shinhs@snucom.snu.ac.kr

Lonnie R. Welch (Chair for the Americas)
Naval Surface Warfare Center
Internet: welch@vienna.njit.edu

Program Vice Chairs:
FAULT TOLERANCE
A. Kanevsky, MITRE
Yoshiaki Kakuda, Osaka University

RUN-TIME SYSTEMS
Ray Clark, OSF
R. Rajkumar, CMU/SEI

ARCHITECTURE AND HARDWARE
P. Ramanathan, University of Wisconsin

COMMUNICATIONS AND NETWORKING
Kenji Toda, Electrotechnical Laboratory, Japan
Ricardo Bettati, Texas A&M University

ANALYSIS, VALIDATION, AND SIMULATION
Guenter Hommel, Technical University of Berlin
Michael W. Masters, Naval Surface Warfare Center

REAL-TIME DATABASES
Sang Son, University of Virginia
Maarten Boasson, Hollands Signaal, The Netherlands

NEW PARADIGMS AND LANGUAGES
Norman R. Howes, Institute for Defense Analyses
Bo Sanden, George Mason University

SYSTEMS ENGINEERING AND REENGINEERING
Bruce Lewis, Army MICOM
Mark Wilson, Naval Surface Warfare Center

FORMAL METHODS
Loe Feijs, Philips Research, The Netherlands
F. Jahanian, University of Michigan
Tomohiro Yoneda, Tokyo Institute of Technology

TOOLS AND ENVIRONMENTS
D. Bhatt, Honeywell
Joerg Kaiser, GMD

MULTIMEDIA
Borko Fuhrt, Florida Atlantic University

Advisory Committee:
Theodore Baker, Florida State University
Alok Choudhary, Syracuse University
Harry Crisp, NSWC
Flaviu Cristian, University of California
Wolfgang Halang, University of Hagen
Robert D. Harrison, NSWC
Mathai Joseph, University of Warwick
Jan van Katwijk, Technical University of Delft, The Netherlands
Gerard LeLann, INRIA, France
Jane Liu, University of Illinois
Miroslav Malek, Humboldt University, Germany
Al Mok, University of Texas at Austin
Jose L. Munoz, ARPA
Viktor K. Prasanna, University of Southern California
Mike G. Rodd, University of Wales Swansea
Karsten Schwan, Georgia Institute of Technology
Kang G. Shin, University of Michigan
Behrooz Shirazi, University of Texas at Arlington
John A. Stankovic, University of Massachusetts
Mario Tokoro, Keio University, Japan
Richard Volz, Texas A&M University
Stephanie White, Northrop/Grumman
Steve Zeigler, Rational Corp.
Wei Zhao, Texas A&M University

Publication Chair:
David L. Andrews, University of Arkansas

Publicity Chairs:
Michael R. Olsem, U.S. Air Force Software Tech. Support Ctr.
Antonio L. Samuel, U.S. Naval Surface Warfare Center
Bradley R. Swim, King Saud University, Saudi Arabia
Jack Verhoosel, Telematic Research Center, The Netherlands

WPDRTS is held in cooperation with the IEEE Technical Committee on Parallel
Processing, the IEEE Technical Committee on Real-Time, and the IEEE Technical
Committee on Engineering of Computer based Systems. The workshop is sponsored
by the Naval Surface Warfare Center Dahlgren Division.

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Workshop 5

Workshop 5: Monday Afternoon and Tuesday Morning

(Tuesday Session Joint with Workshop on Job Scheduling Strategies for Parallel
Processing)

5TH WORKSHOP ON HETEROGENEOUS COMPUTING

Workshop Chair:
Richard Freund, NRaD

Keynote Speaker:
Rick Stevens,
Argonne National Laboratory

-------------------------------------------------------------------------------
Program Committee:

Francine Berman, U.C. San Diego (Chair)
David Culler, U.C. Berkeley
Joan Francioni, University of Southwestern Louisiana
Andrew Grimshaw, University of Virginia
Debbie Hensgen, Naval Postgraduate School
Miron Livny, University of Wisconsin
Reagan Moore, San Diego Supercomputer Center
H.J. Siegel, Purdue University
Vaidy Sunderam, Emory University
Robert Voigt, National Science Foundation
Richard Wolski, U.C. San Diego

Steering Committee:
Francine Berman, U.C. San Diego
Jack Dongarra, University of Tennessee
Richard Freund, NRaD (Chair)
Debbie Hensgen, Naval Postgraduate School
Paul Messina, Center for Advanced Computing Research
Jerry Potter, Kent State University
Viktor Prasanna, University of Southern California
H.J. Siegel, Purdue University
Vaidy Sunderam, Emory University

Heterogeneous Computing is the coordinated use of distributed and potentially
diverse resources to efficiently solve large-scale problems. Applications
implemented on heterogenous platforms achieve performance by aggregating memory
from distributed sources, coordinating distinct data sources, exploiting the
affinity of tasks to diverse computational platforms or paradigms, and/or
coordinating distinct administrative domains.
This year, the 1996 Heterogeneous Computing Workshop will conduct a joint
session with the Workshop on Job Scheduling Strategies for Parallel Processing.
Papers presented during this joint session will target the scheduling of
parallel applications on distributed and heterogenous systems of resources.
Authors are invited to submit manuscripts that demonstrate original unpublished
research in all areas of Heterogeneous Computing. Topics of interest include,
but are not limited to :
- Basic models and performance measures
- Efficient resource management strategies
- Scheduling parallel applications on distributed heterogeneous systems
- Transparent mechanisms for storing and handling data
- System interfaces and programming tools
- Failure resilience strategies
- "Proof of concept" application implementations

To submit a paper to the 1996 Heterogeneous Computing Workshop, please send 11
copies of an extended abstract (not to exceed 10 double-spaced single sided
pages with a 250 word abstract) to:
Francine Berman
Department of Computer Science and Engineering 0114
University of California, San Diego
La Jolla, California 92093
Fax: (619) 534-7029
Internet: berman@cs.ucsd.edu
http://www-cse.ucsd.edu/users/berman/index.html

Indicate in your cover letter if your paper would fit in the joint session.
Manuscripts MUST be received by January 12, 1996. Proceedings will be available
on the World-Wide Web at http://www-cse.ucsd.edu/users/berman/hcw.html and at
the Workshop. For further information, please contact the Workshop Chair:

Richard Freund
Heterogeneous Computing Team
NCCOSC RDTE DIV 4221, Room 341A
53118 Gatchell Road
San Diego, CA 92152-7446
Vox: (619) 553-4071
Internet: freund@nosc.mil


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                               TUESDAY, APRIL 16

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Workshop 6

All Day Tuesday

(Morning Session Joint with Heterogeneous Computing Workshop)

2ND WORKSHOP ON JOB SCHEDULING STRATEGIES FOR PARALLEL PROCESSING

Workshop Co-Chairs:
Dror Feitelson
Hebrew University
Israel

Larry Rudolph, MIT and HU

-------------------------------------------------------------------------------
Program Committee:

Nawaf Bitar, Silicon Graphics
David Black, OSF
Jim Cownie, BBN
Allan Gottlieb, NYU
Scott Hahn, Intel
Mal Kalos, Cornell Theory Center
Phil Krueger, Sequent
Miron Livny, University of Wisconsin
Virginia Lo, University of Oregon
Reagan Moore, SDSC
Ken Sevcik, University of Toronto
Charlie Smith, Cray Research
Mark Squillante, IBM Research
Bernard Traversat, NASA Ames
John Zahorjan, University of Washington
-------------------------------------------------------------------------------

As large parallel computers become more popular, scheduling strategies become
more important as a means of balancing the need for exclusive use of the
machine's resources and the desire to make these resources readily available to
many diverse users. Neither sign-up sheets, naive time-slicing, nor naive
space-slicing are suitable solutions. Moreover, there appears to be a
divergence between what is studied, modeled, and analyzed in academic circles
and the actual, sometimes ad-hoc, scheduling schemes developed by vendors and
large installations.
Continuing the tradition established at IPPS'95, the workshop is intended to
attract people from academia, supercomputing centers, national laboratories,
and parallel computer vendors to address resource management issues in
multiuser parallel systems, and attempt to resolve the conflicting goals such
as short response times for interactive work, minimal interference with batch
jobs, fairness to all users, and high system utilization. We hope to achieve a
balance between reports of current practices in large and heavily-used
installations, proposals of novel schemes that have not yet been tested in a
real environment, and realistic models and analysis. The emphasis will be on
practical designs in the context of real parallel operating systems.
One session will be held jointly with the Heterogeneous Computing Workshop
(HCW). Papers presented during this joint session will target the scheduling of
parallel applications on distributed and heterogenous systems of resources.
Topics of interest include:

- Experience with actual scheduling policies
- Performance implications of scheduling strategies
- Fairness, priorities, and accounting issues
- Workload characterization and classification
- Support for various job classes
- Static vs. dynamic partitioning
- Time slicing, gang, or co-scheduling
- The interaction of computational model on scheduling
- Memory management and I/O scheduling issues
- Load estimation and load balancing
- Scheduling on heterogeneous nodes
- Performance metrics to compare scheduling schemes

Submissions:

Papers should be no longer than 20 pages, including figures and references. All
papers will be reviewed, and a proceedings will be distributed at the workshop.
Please indicate suitability for joint session (with HCW). Also, be sure to note
the name, address, phone and e-mail of a contact author. Send postscript of the
paper by e-mail to
rudolph@theory.lcs.mit.edu or 6 hard copies of the paper to :

Larry Rudolph
MIT Lab for Computer Science
545 Technology Square
Cambridge, MA 02139
Vox: (617) 253-6562
Internet: rudolph@theory.lcs.mit.edu

Important dates:
January 12, 1996 (Submission Deadline)
February 26, 1996 (Notification)
March 22, 1996 (Final Copy Due)
April 16, 1996 (Workshop)

-------------------------------------------------------------------------------

Workshop 7

All Day Tuesday

1ST WORKSHOP ON HIGH-LEVEL PROGRAMMING MODELS AND SUPPORTIVE ENVIRONMENTS

Workshop Chair:
Rudolf G. Hackenberg
Technische Universitaet Muenchen

-------------------------------------------------------------------------------
Program Committee:

Arndt Bode, Technische Universitaet Muenchen
Barbara Chapman, Universitaet Wien, Austria
Michael Gerndt, KFA Juelich, Germany
Hermann Hellwagner, Technische Universitaet Muenchen
Francois Irigoin, Ecole des Mines de Paris
Ulrich Kremer, Rutgers University
Howard A. Sholl, University of Connecticut

One of the key issues to be discussed for a (commercial) break through in
parallel processing, are efficient high-level programming models. Along the
way, models have been established which are more convenient than explicit
message passing and allow higher productivity in programming (e.g HPF and DSM).
In the future, more universal programming models are desirable.
Current implementations of high-level programming models often suffer from low
performance of the generated code, from the lack of high-level programming
tools and their focus on specific application areas. This situation requires
strong research efforts in hardware support, performance optimization
techniques and tools for high level programming models, integration of
languages, applications, and tools into programming environments, and in the
development of concepts for universal programming models. This workshop
(HIPS'96) provides a forum for researchers and commercial developers to meet
and discuss the various hardware and software issues involved in the design and
use of high level programming models and supportive environments. Presentations
cover the areas of :

- Implementation techniques for high-level programming models (e.g., interfaces
to hardware, operating system, run-time system, and compiler)
- Optimization techniques (e.g., automatic techniques in the compiler)
- Performance analysis (e.g., high-level analysis tools and interaction of
performance analysis and program optimization)
- Hardware concepts supporting high-level programming models (e.g., distributed
shared memory)
- Design concepts and implementation aspects of universal programming models

The final workshop program and proceedings will be available via WWW by the end
of February '96
(http://wwwbode.informatik.tu-muenchen.de/~hackenbe/hips96.html). For more
information please check the web or contact the Workshop Chair as follows:

Rudolf G. Hackenberg
Technische Universitaet Muenchen
Institut fuer Informatik
Arcisstrasse 21
D-80290 Munich, Germany
Internet: hackenbe@informatik.tu-muenchen.de
Vox: +49-89-2105-2024
Fax: +49-89-2105-8232

-------------------------------------------------------------------------------

Workshop 8

All Day Tuesday

1ST WORKSHOP ON RANDOMIZED PARALLEL COMPUTING

Workshop Chair:
Sanguthevar Rajasekaran,
University of Florida
(raj@cis.ufl.edu)

-------------------------------------------------------------------------------
Program Committee:
Richard Anderson, UW Seattle
Sandeep Bhatt, Bellcore
Frank Hsu, Fordham University
Phil Klein, Brown University
Danny Krizanc, Carleton University
Tom Leighton, MIT
Bruce Maggs, CMU
Yossi Matias, ATT Bell Labs
Greg Plaxton, UT Austin
Prabhakar Raghavan, IBM Almaden
Sanguthevar Rajasekaran (Chair), Univ. of Florida
Abhiram Ranade, UC Berkeley
John Reif, Duke University
Sartaj Sahni, Univ. of Florida
Sandeep Sen, IIT New Delhi
Uzi Vishkin, Univ. of Maryland and Tel Aviv University
Jeff Vitter, Duke University

Randomization has played a vital role in the domains of both sequential and
parallel computing in the past two decades. This workshop is a forum for
bringing together both theoreticians and practitioners who employ randomized
techniques in parallel computing.
Topics include but are not limited to:

- Network algorithms
- PRAM algorithms
- Architectures
- I/O systems
- Scheduling
- Network fault tolerance
- Reconfigurable networks
- Optical networks
- Various applications
- Programming models and languages
- Implementation experience

Papers of an experimental nature (describing implementation results) are
especially sought. Authors are invited to submit previously unpublished
original papers (that will not be submitted elsewhere) reflecting their current
research results. All submitted papers will be refereed for quality and
originality. Accepted papers will be published in the workshop proceedings.
Authors are requested to submit six copies of the manuscripts to :

S. Rajasekaran,
Dept. of CISE,
301 CSE Building,
Univ. of Florida,
Gainesville, FL 32611
USA

by December 1. Late submissions run the risk of rejection without consideration
of merits. Each manuscript should be of length no more than 12 double-spaced
single sided pages using 12 point type.
Important Dates:
December 1, 1995 (Submissions Due )
February 1, 1996 (Notification)
March 5, 1996 (Camera Ready Manuscripts Due)

-------------------------------------------------------------------------------

Workshop 9

All Day Tuesday

2ND WORKSHOP ON SOLVING IRREGULAR PROBLEMS ON DISTRIBUTED MEMORY MACHINES

Workshop Chair:
Sanjay Ranka
University of Florida
-------------------------------------------------------------------------------

Program Committee:

Prith Banerjee, University of Illinois
Geoffrey Fox, Syracuse University
Apostolos Gerasoulis, Rutgers University
Vipin Kumar, University of Minnesota
Viktor K. Prasanna, University of Southern California
Jose Rolim, University of Geneva
Ponnuswamy Sadayappan, Ohio State University
Sartaj Sahni, University of Florida
Tao Yang, University of California at Santa Barbara
Kathy Yelick, University of California at Berkeley

This is the second year of this workshop. This workshop will focus on
architectures, algorithms, programming models, and languages for efficiently
solving large irregular problems on parallel machines with distributed memory.
These include machines with and without hardware support for multithreading,
message passing, and shared memory.
The workshop will feature invited papers, contributed papers, and panel
sessions in an informal setting. Proceedings of the first workshop is available
at:
http://www.cis.ufl.edu/~ranka.

The workshop is sponsored by the IEEE Technical Committee on Parallel
Processing. For further information, please contact:

Sanjay Ranka
Department of CISE
301 CSE Bldg
University of Florida, FL 32611, USA
Internet: ranka@cis.ufl.edu

To submit a paper for consideration, please send six copies to Sanjay Ranka by
January 31, 1996. The final camera ready manuscripts are due March 20, 1996.
Electronic submissions (postscript versions) are encouraged.

-------------------------------------------------------------------------------

Workshop 10

All Day Tuesday

2ND WORKSHOP ON HIGH-SPEED NETWORK COMPUTING (HiNet '96)

Workshop Co-Chairs:
H.M. Alnuweiri,
University of British Columbia
(hussein@ee.ubc.ca)

M. Hamdi
Hong Kong University of
Science and Technology
(hamdi@cs.ust.hk)
-------------------------------------------------------------------------------

Program Committee:

S. Chanson, Hong Kong Univ. of Science and Technology
P.W. Dowd, State University of New York, Buffalo
D.H.C. Du, University of Minnesota
R.G. Hackenberg, Technical University of Munich
B. Hamidzadeh, Hong Kong Univ. of Science and Technology
S. Hariri, Syracuse University
M.R. Ito, University of British Columbia
R. Jain, Ohio State University
T.V. Lakshman, Bell Communications Research
W.T. O'Connell, AT&T Bell Laboratories
C.S. Raghavendra, Washington State University
T. Szymanski, McGill University
H. Xu, USC Information Sciences Institute

High-speed networking is viewed by the information processing and
telecommunications communities as the next major infrastructure industry.
High-speed networks (such as Sonet/ATM and high-speed LANs) can be used for
interconnecting a large number of (possibly distant) autonomous computers that
operate in a distributed computing environment. The main theme of this workshop
centers on the impact of the emerging technology of high-speed networks in the
area of high performance parallel and distributed computing. Contributions to
HiNet '96 explore the capabilities, point the difficulties, and report on the
experience with high speed networks when employed in distributed computing
environments. The presentations will cover the following topics:

- Computing paradigms for high-speed networks
- High-speed network protocols for parallel and distributed processing
- Programming environments and tools for high-speed network computing
- Performance evaluation and simulation
- Experimentations and test-beds
- Architecture and topology of high-speed networks
- Switching and routing techniques
- Distributed data-base design and processing on high-speed networks
- Scheduling and load balancing aspects of high-speed network computing
- Efficient communication interfaces
- Mobile computing
- Mapping parallel algorithms onto high-speed networks
- Algorithm design and analysis for high-speed networks
- Applications and software tools

For further information, please contact any of the Co-Chairs. To submit a
paper, send four copies of your complete manuscript (not to exceed 20 double
spaced pages) to one of the Workshop Co-Chairs. Please e-mail addresses as well
as fax and phone numbers.
Important Dates:
January 21, 1996 (Complete Submission Due)
February 21, 1996 (Notification of Acceptance)
March 20, 1996 (Final Copy Due) Further details are available from the Web at
URL http://www.cs.ust.hk/Postings/Hinet.html.

-------------------------------------------------------------------------------

Tutorial 1

9:00 AM - 1:00 PM

AN INTRODUCTION TO THE MESSAGE-PASSING INTERFACE (MPI)
Bill Gropp,
Argonne National Laboratory

Marc Snir,
IBM T.J. Watson Research Center

David Walker,
Oak Ridge National Laboratory
-------------------------------------------------------------------------------

Who Should Attend:
This tutorial will mostly benefit researchers with some experience writing
applications using message passing. However, since all aspects of MPI will be
covered, the course will also be of interest to novices. Those interested in
developing software subsystems (compilers, libraries, tools) for use on
message-passing computers will also benefit from attending.

Course Description:
MPI is a standard for message passing that was developed by an open forum in
the last few years. MPI is widely used, is available in public domain
implementations for scalable computers and networks of workstations, and is or
will soon be supported by all major vendors of scalable parallel systems.
This tutorial will describe the features of the MPI message-passing standard
and will show how to use MPI in applications. The course will be divided into
four parts:

1. Overview of MPI, how it came about, and its basic point-to-point and
collective communication capabilities.
2. Advanced features in MPI, in particular, the management of groups and
communication contexts, and use of derived data types, persistent comm
3. Application kernels and examples written using MPI.
4. Recent developments, including MPI implementations and topics being
considered for MPI-2.

The tutorial is based on the following two books:
"Using MPI: Portable Parallel Programming with the Message-Passing Interface,"
William Gropp, Ewing Lusk, and Anthony Skjellum (MIT Press, 1994).
"MPI: the Complete Reference," Marc Snir, Steve Otto, Steven Huss-Lederman,
David Walker, and Jack Dongarra (MIT Press, 1995).

Lecturers:
Bill Gropp is a scientist in the Mathematics and Computer Science Division at
Argonne National Laboratory. He was one of the most active members of the MPI
forum that designed the Message Passing Interface, and is coauthor of "Using
MPI."
Mark Snir is a senior manager at the IBM T.J. Watson Research Center where he
leads research on scalable parallel software and scalable parallel
architectures. He was involved in the design and initial development of the
parallel operating environment for the IBM SP1 and SP2; he wrote large parts of
the MPI standard and is involved in IBM's MPI development; and he is a coauthor
of "MPI: the Complete Reference."
David Walker is a senior member of the research staff in the Mathematical
Sciences Section at Oak Ridge National Laboratory and an adjunct associate
professor in the Department of Computer Science of the University of Tennessee,
Knoxville. His research interests include the development of software
libraries, algorithms, and applications for high performance computers. He is a
frequent lecturer on MPI and coauthor of "MPI: the Complete Reference."

-------------------------------------------------------------------------------

Tutorial 2

2:00 PM - 6:00 PM

INTRODUCTION TO PARALLEL AND DISTRIBUTED SIMULATION TECHNIQUES WITH
APPLICATIONS TO VLSI, MULTIPROCESSOR ARCHITECTURES, AND MOBILE
TELECOMMUNICATION SYSTEMS
Sushil K. Prasad,
Georgia State University, Atlanta

Sajal K. Das,
University of North Texas, Denton
-------------------------------------------------------------------------------

Who Should Attend:
The audience may include engineers, computer professionals and simulationists
interested in transferring the parallel simulation technology to their
application domains, graduate students and advanced researchers interested in
the challenging open problems in this growing area, and educators who are
looking for large-scale non-numeric applications on which their students can
successfully apply parallel computing skills. An understanding of the basic
parallel processing concepts will be assumed, but no background in simulation
or modeling is required.

Course Description:
Large-scale and complex simulation applications such as VLSI logic circuits,
computer architectures, communication networks, and battlefield management have
increasingly become too slow on uniprocessor computers due to their excessive
computational needs. Parallel and distributed simulation techniques offer a
viable alternative, and they have been the focus of research and development in
the past decade. As a result, several important discrete event systems in
varied areas have been successfully simulated with demonstrated speedups.
This tutorial will introduce proven techniques in parallelizing large and
complex discrete event simulations on popular computing platforms including
network of workstations, shared-memory multiprocessors, and large
message-passing multicomputers. Existing parallel simulations in several
application areas would be used for case studies.
We will present state-of-the-art concepts and various challenges involved in
parallelizing simulations, and discuss the associated techniques and algorithms
which have been found to be very useful in practice. Topics will include an
introduction to sequential discrete event simulation, the basic approaches of
parallel simulation including conservative, optimistic and time-driven schemes,
their applications, designing and implementing your own parallel simulator,
evolving methods, and the outstanding problems.

Lecturers:
Sushil K. Prasad is an Assistant Professor in Mathematics and Computer Science
Department at Georgia State University. He has been actively involved with
research in parallel and distributed simulation for the past seven years. His
expertise includes parallel simulation of VLSI logic circuits and battlefield
management, parallel data structures for priority queues, and parallel
algorithms for graph and other non-numeric problems.
Sajal K. Das is an Associate Professor of Computer Sciences and also the
Director of the Center for Research in Parallel and Distributed Computing at
the University of North Texas, Denton. Over the past ten years, he has been an
active researcher in the area of parallel processing and architectures such as
parallel algorithm design, parallel simulation, interconnection networks, load
balancing and dynamic mapping of irregularly structured problems on
multicomputers. His current research interests also include cellular mobile
computing. He serves on the Editorial Boards of Parallel Processing Letters,
Journal of Parallel Algorithms and Applications, and CD-ROM Journal of
Computing.


-------------------------------------------------------------------------------

                              WEDNESDAY, APRIL 17

-------------------------------------------------------------------------------

Keynote Address

8:00 AM - 9:00 AM
Can Multithreaded Programming save Massively Parallel Computing?
Charles E. Leiserson
Massachusetts Institute of Technology

Session 1

9:30 AM - 11:30 AM

Compiler Optimization
Chair: Prith Banerjee
University of Illinois, Urbana
-------------------------------------------------------------------------------

Eliminating Stale Data References through Array Data-Flow Analysis
Lynn Choi, University of Illinois, Urbana,
Pen-Chung Yew, University of Minnesota, Minneapolis

Commutativity Analysis: A New Technique for Automatically Parallelizing
Pointer-Based Computations
Martin C. Rinard and Pedro Diniz,
University of California, Santa Barbara

Profiling Dependence Vectors for Loop Parallelization
Shaw-Yen Tseng, Chung-Ta King, and Chuan-Yi Tang,
National Tsing Hua University

A Method for Optimal Register Allocation to Loops in Multiple Register File
Architectures
David J. Kolson, Alexandru Nicolau, and Nikil Dutt, University of California,
Irvine,
Ken Kennedy, Rice University

Towards Automating Unimodular Transformations for Imperfect Loop Nests
Jingling Xue, University of New England

The Combined Effectiveness of Unimodular Transformations, Tiling, and Software
Prefetching
Rafael H. Saavedra, Weihua Mao, Daeyeon Park, Jacqueline Chame, and Sungdo
Moon,
University of Southern California

-------------------------------------------------------------------------------

Session 2

9:30 AM - 11:30 AM

Scientific/Engineering Applications
Chair: Jose D.P. Rolim
University of Geneva
-------------------------------------------------------------------------------

Ocean Circulation on the Intel Paragon: Modeling and Implementation --Ka-Cheong
Leung and Ishfaq Ahmad, Hong Kong University of Science and Technology,
Hsiao-Ming Hsu, National Center for Atmospheric Research

Implementation of Automatic Semi-Fluid Motion Analysis Algorithm on a Massively
Parallel Computer --Mohammad Faisal, K. Palaniappan, Chandra Kambhamettu, and
A. Frederick Hasler, NASA Goddard Space Flight Center

NAS Experiences of Porting CM Fortran Codes to HPF on IBM SP2 and SGI Power
Challenge --Subhash Saini, NASA Ames Research Center

Dynamic Alignment and Distribution of Irregularly Coupled Data Arrays for
Scalable Parallelization of Particle-in-Cell Problems --Wei-Keng Liao, Chao-Wei
Ou, and Sanjay Ranka, Syracuse University

A Hierarchical Parallel Processing System for the Multipass-Rendering Method
--Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, and Tadao Nakamura, Tohoku
University

Performance Modeling and Composition: A Case Study in Cell Simulation --Steve
G. Steinberg, Jun Yang, and Katherine Yelick, University of California,
Berkeley

-------------------------------------------------------------------------------

Session 3

9:30 AM - 11:30 AM

Distributed Memory Systems
Chair: Behrooz Shirazi
University of Texas, Arlington
-------------------------------------------------------------------------------

     A Study of High Performance Communication Mechanism for Multicomputer
     Systems --Hideki Murayama, Satoshi Yoshizawa, Takeshi Aimoto, Hidenori
     Inouchi, Shooichi Murase, Takehisa Hayashi, and Hirosh Iwamoto, Hitachi,
     Ltd.

     A TeraFLOP Supercomputer in 1996: the ASCI TFLOPS System --Timothy G.
     Mattson, David Scott, and Stephen Wheat, Intel Corporation

     Experience with Parallel Computing on the AN2 Network --Daniel J. Scales,
     Stanford University, Michael Burrows and Chandramohan A. Thekkath, DEC
     Systems Research Center

     Achieving a Balanced Low-Cost Architecture for Mass Storage Management
     through Multiple Fast Ethernet Channels on the Beowulf Parallel
     Workstation --Thomas Sterling, NASA Goddard Space Flight Center and
     University of Maryland, Donald Becker, NASA Goddard Space Flight Center,
     Daniel Savarese,

     Exploiting the Capabilities of Communications Co-Processors --Klaus E.
     Schauser, Chris J. Scheiman, J. Mitchell Ferguson, and Paul Z. Kolano,
     University of California, Santa Barbara

     Effects of Multithreading on Data and Workload Distribution for
     Distributed-Memory Multiprocessors --A. Sohn, New Jersey Institute of
     Technology, M. Sato, Electrotechnical Laboratory, N. Yoo and J.-L.
     Gaudiot, University of Southern California

-------------------------------------------------------------------------------

Session 4

2:30 PM - 4:30 PM

Shared Memory Systems
Chair: Rudolf G. Hackenberg
Technische Universitaet Muenchen
Institut fuer Informatik
-------------------------------------------------------------------------------

     Formal Verification of Delayed Consistency Protocols --Fong Pong, Sun
     Microsystems Computer Corporation, Michel Dubois, University of Southern
     California

     Dag-Consistent Distributed Shared Memory --Robert D. Blumofe, Matteo
     Frigo, Christopher F. Joerg, Charles E. Leiserson, and Keith H. Randall,
     Massachusetts Institute of Technology

     Categorizing Network Traffic in Update-Based Protocols on Scalable
     Multiprocessors --Ricardo Bianchini, Thomas J. LeBlanc, and Jack Veenstra,
     University of Rochester

     Implementing the Data Diffusion Machine Using Crossbar Routers --Henk L.
     Muller, Paul W.A. Stallard, and David H.D. Warren, University of Bristol

     A Memory Controller for Improved Performance of Streamed Computations on
     Symmetric Multiprocessors --Sally A. McKee and Wm. A. Wulf, University of
     Virginia, Charlottesville

     Kiloprocessor Extensions to SCI --Stefanos Kaxiras, University of
     Wisconsin, Madison

-------------------------------------------------------------------------------

Session 5

2:30 PM - 4:30 PM

Algorithms
Chair: Joseph JaJa
University of Maryland
-------------------------------------------------------------------------------

     Approximate Compaction and Padded-Sorting on Exclusive Write PRAMs
     --Miroslaw Kutylowski, Universitat-GH Paderborn, Tomasz Wierzbicki,
     Uniwersytet Wroclawski

     A Parallel Solution to the Extended Set Union Problem with Unlimited
     Backtracking --Vincenzo A. Crupi and Christina Pinotti, Consiglio
     Nazionale delle Ricerche, Sajal K. Das, University of North Texas

     A Parallel Algorithm for Minimization of Finite Automata --B. Ravikumar
     and X. Xiong, University of Rhode Island, Kingston

     A Randomized Algorithm for Voronoi Diagram of Line Segments on Coarse
     Grained Multiprocessors --Xiaotie Deng, York University, Binhai Zhu, Los
     Alamos National Lab.

     Self-Timed Resynchronization: A Post-Optimization for Static
     Multiprocessor Schedules --Shuvra S. Bhattacharyya, Hitachi America
     Limited, Sundararajan Sriram and Edward Lee, University of California,
     Berkeley

     Constructing the Spanners of Graphs in Parallel --Weifa Liang and Richard
     P. Brent, The Australian National University, Canberra

-------------------------------------------------------------------------------

Session 6

2:30 PM - 4:30 PM

Programming Languages
Chair: Gul Agha
University of Illinois, Urbana
-------------------------------------------------------------------------------

     Converse: An Interoperable Framework for Parallel Programming --Laxmikant
     V. Kale, Milind Bhandarkar, Narain Jagathesan, and Sanjeev Krishnan,
     University of Illinois, Urbana

     Dome: Parallel Programming in a Distributed Computing Environment --Jose
     Nagib Cotrim Arabe, Adam Beguelin, Bruce Lowekamp, Erik Seligman, Mike
     Starkey, and Peter Stephan, Carnegie Mellon University

     Nested Parallel Call Optimization --Enrico Pontelli and Gopal Gupta, New
     Mexico State University

     The Parallel Break Construct --Yair I. Friedman, Dror G. Feitelson, and
     Iaakov Exman, The Hebrew University of Jerusalem

     Processor-Oriented Optimizations for Fine-Grained COOP Languages on
     Distributed Memory Machines --Xingbin Zhang, Vijay Karamcheti, Tony Ng,
     and Andrew A. Chien, University of Illinois, Urbana-Champaign

     Support for Extensibility and Reusability in a Concurrent Object-Oriented
     Programming Language --Raju Pandey, University of California, Davis, J.C.
     Browne, University of Texas, Austin

-------------------------------------------------------------------------------

Session 7

5:00 PM - 7:00 PM

Communication-I
Chair: Cho-Li Wang
University of Hong Kong

     Modeling the Communication Performance of the IBM SP2 --Gheith A. Abandah
     and Edward S. Davidson, University of Michigan, Ann Arbor

     Adaptive Source Routing in Multicomputer Interconnection Networks --Yucel
     Aydogan, Bilkent University, Craig B. Stunkel, IBM T.J. Watson Research
     Center, Cevdet Aykanat, Bilkent University, Bulent Abali, IBM T.J Watson
     Research Center

     The Effects of Network Contention on Processor Allocation Strategies
     --Sherry Q. Moore and Lionel M. Ni, Michigan State University

     ServerNet Deadlock Avoidance and Fractahedral Topologies --Robert W.
     Horst, Tandem Computers Incorporated

     Analysis of Memory Interference in Buffered Multiprocessor Systems in
     Presence of Hot Spots and Favorite Memories --Sajal K. Das and Sanjay K.
     Sen, University of North Texas

     Benefits of Processor Clustering in Designing Large Parallel Systems: When
     and How? --D. Basak, D.K. Panda, and M. Banikazemi, The Ohio State
     University, Columbus

-------------------------------------------------------------------------------

Session 8

5:00 PM - 7:00 PM

Implementation of Primitive Operations
Chair: Gregory Plaxton
University of Texas, Austin
-------------------------------------------------------------------------------

     Practical Parallel Algorithms for Dynamic Data Redistribution, Median
     Finding, and Selection --David A. Bader and Joseph JaJa, University of
     Maryland, College Park

     Parallel Implementation of Boruvka's Minimum Spanning Tree Algorithm --Sun
     Chung and Anne Condon, University of Wisconsin, Madison

     Practical Algorithms for Selection on Coarse-Grained Parallel Computers
     --Ibraheem Al-furiah, Srinivas Aluru, Sanjay Goil, and Sanjay Ranka,
     Syracuse University

     Parallel Multilevel Graph Partitioning --George Karypis and Vipin Kumar,
     University of Minnesota, Minneapolis

     PACK/UNPACK on Coarse-Grained Distributed Memory Parallel Machines
     --Seung-Jo Bae, Syracuse University, Sanjay Ranka, University of Florida,
     Gainesville

     Random Seeking: A General, Efficient, and Informed Randomized Scheme for
     Dynamic Load Balancing --Nihar R. Mahapatra and Shantanu Dutt, University
     of Minnesota, Minneapolis

-------------------------------------------------------------------------------

Session 9

5:00 PM - 7:00 PM

Resource Allocation and Management
Chair: Rafael H. Saavedra
University of Southern California
-------------------------------------------------------------------------------

     Resource Placement in Torus-Based Networks --Myung M. Bae and Bella Bose,
     Oregon State University, Corvallis

     Simultaneous Compression of Makespan and Number of Processors Using CRP
     --Yigun Ge and David Y.Y. Yun, University of Hawaii, Honolulu

     Implementation of Scalable Blocking Locks Using an Adaptive Thread
     Scheduler --Bodhisattwa Mukherjee, IBM T.J. Watson Research Center,
     Karsten Schwan, Georgia Institute of Technology

     Hector: Automated Task Allocation for MPI --Samuel H. Russ, Brian Flachs,
     Jonathan Robinson, and Bjorn Heckel, Mississippi State University

     Adaptive Data Placement for Distributed-Memory Machines --David K.
     Lowenthal and Gregory R. Andrews, The University of Arizona, Tucson

     Complete Parallelization of Computations: Integration of Data Partitioning
     and Functional Parallelism for Dynamic Data Structures --J.C. Browne and
     Dwip Banerjee, University of Texas, Austin

-------------------------------------------------------------------------------
7:00 PM - 9:00 PM IPPS "Open House" (Details to be announced)

-------------------------------------------------------------------------------


-------------------------------------------------------------------------------

                               THURSDAY, APRIL 18

-------------------------------------------------------------------------------

Keynote Address

8:00 AM - 9:00 AM
MPPs versus Clusters
Charles L. Seitz, Myricom, Inc.

-------------------------------------------------------------------------------

Session 10

9:30 AM - 11:30 AM

Communication-II
Chair: Louise Moser
University of California, Santa Barbara
-------------------------------------------------------------------------------

     Generating Realignment-Based Communication for HPF Programs --Tsunehiko
     Kamachi, Kazuhiro Kusano, Kenji Suehiro, Yoshiki Seo, Masanori Tamura, and
     Shoichi Sakon, NEC Corporation

     Software Support for Virtual Memory-Mapped Communication --Cezary
     Dubnicki, Liviu Iftode, Edward W. Felten, and Kai Li, Princeton University

     How to Optimize Residual Communications? --Michele Dion, Cyril
     Randriamaro, and Yves Robert, Ecole Normale Superieure de Lyon

     A Comparative Study of Methods for Time-Deterministic Message Delivery in
     a Multiprocessor Architecture --Jan Jonsson and Jonas Vasell, Chalmers
     University of Technology

     ECO: Efficient Collective Operations for Communication on Heterogeneous
     Networks --Bruce B. Lowekamp and Adam Beguelin, Carnegie Mellon University

     Software Techniques for Improving MPP Bulk-Transfer Performance --Eric A.
     Brewer, Paul Gauthier, and Armando Fox, University of California, Berkeley

-------------------------------------------------------------------------------

Session 11

9:30 AM - 11:30 AM

Algorithms - Implementation
Chair: Mikhail Atallah
Purdue University
-------------------------------------------------------------------------------

     Parallel Algorithms for Image Enhancement and Segmentation by Region
     Growing with an Experimental Study --David A. Bader, Joseph JaJa, David
     Harwood, and Larry S. Davis, University of Maryland, College Park

     The Chessboard Distance Transform and the Medial Axis Transform are
     Interchangeable --Yu-Hua Lee and Shi-Jinn Horng, National Taiwan Institute
     of Technology

     Parallel Algorithm for Image Processing: Practical Algorithms with
     Experiments --Armin Baumker and Wolfgang Dittrich, University of Paderborn

     Study of Scalable Declustering Algorithms for Parallel Grid Files --Bongki
     Moon, Anurag Acharya, and Joel Saltz, University of Maryland, College Park

     A Parallel Algorithm for Text Inferring --Sanda M. Harabagiu, University
     of Southern California, Dan I. Moldovan, Southern Methodist University

     Special Block-Five-Diagonal System Solvers for the VLSI Parallel Model
     --Marian Vajtersic, Slovak Academy of Sciences

-------------------------------------------------------------------------------

Session 12

9:30 AM - 11:30 AM

Performance Evaluation and Prediction
Chair: John Gustafson
Ames Laboratory
-------------------------------------------------------------------------------

     Efficient Execution of Parallel Applications in Multiprogrammed
     Multiprocessor Systems --Kelvin K. Yue and David J. Lilja, University of
     Minnesota, Minneapolis

     The Relation of Scalability and Execution Time --Xian-He Sun, Louisiana
     State University

     Maximizing Speedup through Self-Tuning of Processor Allocation --Thu D.
     Nguyen, Raj Vaswani, and John Zahorjan, University of Washington, Seattle

     Profiling Optimized Code: A Profiling System for an HPF Compiler --Shaun
     Kaneshiro and Tatsuya Shindo, Fujitsu Limited

     Toward Symbolic Performance Prediction of Parallel Programs --Thomas
     Fahringer, University of Vienna

     Performance Prediction with Benchmaps --Sivan Toledo, IBM T.J. Watson
     Research Center

-------------------------------------------------------------------------------

INDUSTRIAL TRACK

-------------------------------------------------------------------------------

INVITED VENDOR PRESENTATIONS

Industrial Track Chair:John K. Antonio
Texas Tech University

9:30 AM - 11:30 AM
INDUSTRIAL TRACK
Session-I
Parallel Architectures:
Implementation, Programming, and Performance
Session Chair: John K. Antonio ,Texas Tech University
-------------------------------------------------------------------------------
Cray Research, Inc.
Topic: Communication Latency and Bandwidth on the Cray Research T3E
Author: Frank W. Chism, Senior Analyst

IBM System/390 Division
Topic: Overview of IBM System/390 Parallel Sysplex:
A Commercial Parallel Processing System
Authors: Jeffrey M. Nick, Chief Architect System/390 Parallel Sysplex,
Dave Surman, Chief Design System/390 Parallel Sysplex,
Jen-Yao Chung, Research Scientist/Manager, and
Nicholas S. Bowen, Research Scientist/Senior Manager

Litton Guidance and Control Systems, Inc.
Topic: Implementing Parallel Processing in a Rugged Embeddable Environment
Author: Alan L. Smeyne, Manager, Business Development

Mercury Computer Systems, Inc.
Topic: Message Passing Using Planned Data Transfers
Authors: Arlan Pool, Advanced Product Planning and Craid Lund, Principal
Technologist

2:30 PM - 4:30 PM
INDUSTRIAL TRACK
Session-II
Networking and Distributed Computing
Session Chair: Richard C. Metzger, Rome Laboratory

Centre for Development of Advanced Computing
Topic: DS-Link over Fiber: A High Speed Interconnect for Cluster Computing
Authors: Yogindra Abhyankar, Member Technical Staff,
Anil Degwekar, Member Technical Staff, and
Abhay Karandikar, Member Technical Staff

Electronics and Telecommunications Research Institute
Topic: A Multiprocessor Server with a New Highly Pipelined Bus
Authors: Woo-Jong Hahn, Principal Member of Engineering Staff,
An-Do Ki, Senior Member of Engineering Staff,
Ki-Wook Rim, Director of Computer Systems Department, and
Soo-Won Kim, Professor of Electronics Engineering (Korea University)

Tandem Computers Incorporated
Topic: Performance Modeling of ServerNet Topologies
Authors: Robert Wilkinson, Research Assistant (Texas A&M University),
Dimiter R. Avresky, Associate Professor of Computer Science (Texas A&M
University),
Bob Horst, Technical Director of Tandem Labs,
Doug Jewett, Member of Tandem Labs,
William Watson, Member of Arch/Perf & Design Validation, and
Luke Young, Member of System Verification

Virtual Computer Corporation
Topic: Distributed Virtual Computing
Authors: John Schewel, Vice President of Sales & Marketing,
Michael Thornburg, Vice President of Operations, and
Steve Casselman, President

-------------------------------------------------------------------------------

Session 13

2:30 PM - 4:30 PM

Synchronization, Virtual Memory, and Runtime System Support
Chair: Francine Berman
University of California, San Diego
-------------------------------------------------------------------------------

     CoCheck: Checkpointing and Process Migration for MPI --Georg Stellner,
     Institut fur Informatik der Technischen Universitat Munchen

     A Portable Run-Time System for Object-Parallel Systems --Peter Beckman and
     Dennis Gannon, Indiana University

     A Virtual Memory Model for Parallel Supercomputers --Veronica L.M. Reis
     and Isaac D. Scherson, University of California, Irvine

     A Partitioning Programming Environment for a Novel Parallel Architecture
     --Reiner W. Hartenstein, Jurgen Becker, and Rainer Kress, University of
     Kaiserslautern

     An Integrated Synchronization and Consistency Protocol for the
     Implementation of a High-Level Parallel Programming Language --Martin C.
     Rinard, University of California, Santa Barbara

     Implementation and Evaluation of Prefetching in the Intel Paragon Parallel
     File System --Meenakshi Arunachalam, Alok Choudhary, and Brad Rullman,
     Syracuse University

-------------------------------------------------------------------------------

Session 14

2:30 PM - 4:30 PM

Arrays and Hypercubes
Chair: Oscar Ibarra
University of California, Santa Barbara
-------------------------------------------------------------------------------

     Routing a Permutation in the Hypercube by Two Sets of Edge Disjoint Paths
     --Qian-Ping Gu, The University of Aizu, Hisao Tamaki, IBM Japan

     Determining Asynchronous Acyclic Pipeline Execution Times --Val Donaldson
     and Jeanne Ferrante, University of California, San Diego

     Distributing Tokens on a Hypercube without Error Accumulation --Bogdan S.
     Chlebus, Uniwersytet Warszawski, Jos D.P. Rolim, Universite de Geneve,
     Giora Slutzki, Iowa State University, Ames

     On Some Global Operations in Faulty SIMD Hypercubes --Amit Sengupta and
     C.S. Raghavendra, Washington State University, Pullman

     An Improved Approximation Algorithm for Scheduling Task Trees on Linear
     Arrays --Hari Krishna Tadepalli and Errol L. Lloyd, University of Delaware

     Mapping Linear Recurrences onto Systolic Arrays --Ladan Kazerouni,
     University of Bombay, Basant Rajan and R.K. Shyamasundar, Tata Institute
     of Fundamental Research

-------------------------------------------------------------------------------

Session 15

2:30 PM - 4:30 PM

Mathematical Methods
Chair: Dan I. Moldovan
Southern Methodist University
-------------------------------------------------------------------------------

     Jacobi-like Algorithms for Eigenvalue Decomposition of a Real Normal
     Matrix Using Real Arithmetic --B.B. Zhou and R.P. Brent, The Australian
     National University, Canberra

     An Element-Based Concurrent Partitioner for Unstructured Finite Element
     Meshes --Hong Q. Ding and Robert D. Ferraro, Jet Propulsion Laboratory

     Analysis of the Numerical Effects of Parallelism on a Parallel Genetic
     Algorithm --William E. Hart, Sandia National Laboratories, Scott Baden,
     Richard K. Belew, and Scott Kohn, University of California, San Diego

     Compiling MATLAB Programs to SCALAPACK: Exploiting Task and Data
     Parallelism --Shankar Ramaswamy, Eugene W. Hodges IV, and Prithviraj
     Banerjee, University of Illinois, Urbana-Champaign

     Mapping Techniques for Parallel Evaluation of Chains of Recurrences
     --Eugene V. Zima, Moscow State University, Karthi R. Vadivelu and Thomas
     L. Casavant, University of Iowa, Iowa City

     Performance of Asynchronous Linear Iterations with Random Delays --Adrian
     C. Moga and Michel Dubois, University of Southern California

-------------------------------------------------------------------------------

Panel Session

5:00 PM - 7:00 PM
For a Massive Number of Massively Parallel Machines: What Are the Target
Applications, Who Are the Target Users, and What New R&D is Needed to Hit the
target???
-------------------------------------------------------------------------------

Moderator:
H.J. Siegel, Purdue University

Panelists:
William Farmer, Integrated Computing Engines, Inc.
Richard Freund, NRaD
Mark Furtney, Cray Research, Inc.
Paul Messina, Caltech
Lionel M. Ni, National Science Foundation
Charles L. Seitz, Myricom, Inc.
Marc Snir, IBM T. J. Watson Research Center

Description:
If it is assumed, for discussion's sake, that "massive" means at least one
thousand, there are probably at most one or two hundred massively parallel
machines (i.e machines with at least one thousand processors).

- What (if any) APPLICATION AREAS can make possible the existence of a
"massive" number of massively parallel machines in the 5 to 10 year time frame?

- Who are the USERS that need massively parallel machines to perform these
applications?

- What should the parallel processing RESEARCH and INDUSTRIAL communities do to
facilitate the use of parallel machines for these applications and users? That
is, what are the PARTICULAR application domains that will lead to MASSIVE sales
of massively parallel machines, what SPECIFIC software and hardware advances
are needed for these applications, and PRECISELY who are the customers that
should be pursued?

-------------------------------------------------------------------------------


-------------------------------------------------------------------------------

                                FRIDAY, APRIL 19

-------------------------------------------------------------------------------

Keynote Address

8:00 AM - 9:00 AM
-------------------------------------------------------------------------------

Clusters for Commercial Computing: An Invisible Architecture
Gregory F. Pfister,
IBM Server Group, Austin
-------------------------------------------------------------------------------

Session 16

9:30 AM - 11:30 AM

Interconnection Networks
Chair: D.K. Panda
Ohio State University
-------------------------------------------------------------------------------

     Generic Methodologies for Deadlock-Free Routing --Hyunmin Park and Dharma
     P. Agrawal, North Carolina State University

     Partitionability of the Multistage Interconnection Networks --Yeimkuan
     Chang, Chun-Hua Politechnic Institute

     On Embedding Various Networks into the Hypercube Using Matrix
     Transformations --M. Hamdi and S.W. Song, Hong Kong University of Science
     and Technology

     Optimal Subcube Fault Tolerance in a Circuit-Switched Hypercube --Baback
     A. Izadi and Fusun Ozguner, The Ohio State University, Columbus

     Fault-Tolerant Ring Embedding in Star Graphs --Yu-Chee Tseng, Chung-Hua
     Polytechnic Institute, Shu-Hui Chang and Jang-Ping Sheu, National Central
     University

     An Optical Interconnect Model for k-ary n-cube Wormhole Networks --Mongkol
     Raksapatcharawong and Timothy Mark Pinkston, University of Southern
     California

-------------------------------------------------------------------------------

Session 17

9:30 AM - 11:30 AM

Bus-Based Algorithms
Chair: Sartaj Sahni
University of Florida
-------------------------------------------------------------------------------

     Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms --Ramachandran
     Vaidyanathan and Sudharani Nadella, Louisiana State University, Baton
     Rouge

     Coping with Sparse Inputs on Enhanced Meshes - Semigroup Computation with
     COMMON CRCW Buses --Peter Damaschke, Fern Universitat

     An Optimal Algorithm for the Angle-Restricted All Nearest Neighbor Problem
     on the Reconfigurable Mesh, with Applications --Koji Nakano, Nagoya
     Institute of Technology, Stephan Olariu, Old Dominion University

     Parallel Algorithms Using Unreliable Broadcasts --John Matthews and
     Charles Martel, University of California, Davis

     Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable
     Optical Buses --Sandy Pavel and Selim G. Akl, Queen's University

     Integer and Floating Point Matrix-Vector Multiplication on the
     Reconfigurable Mesh --Jerry L. Trahan, Chun-Ming Lu, and Ramachandran
     Vaidyanathan, Louisiana State University

-------------------------------------------------------------------------------

Session 18

9:30 AM - 11:30 AM

Image and Radar Processing
Chair: D. Martinez
MIT Lincoln Laboratory
-------------------------------------------------------------------------------

     Some Image Processing Algorithms on a RAP with Wider Bus Networks
     --Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, and Yu-Hua Lee,
     National Taiwan Institute of Technology

     Parallel Synthetic Aperture Radar Processing on Workstation Networks
     --Peter G. Meisl and Mabo R. Ito, University of British Columbia

     The Evolution of a Massively Parallel Vision System for Real-Time
     Automotive Image Processing --Alberto Broggi, Universita di Parma

     2D Object Recognition on a Reconfigurable Mesh --Concettina Guerra, Purdue
     University and Universita di Padova

     Space-Time Adaptive Processing on the Mesh Synchronous Processor --Janice
     S. McMahon and Ken Teitelbaum, MIT Lincoln Laboratory

     An Experimental Study of Input/Output Characteristics of NASA Earth and
     Space Sciences Applications --Michael R. Berry and Tarek A. El-Ghazawi,
     The George Washington University

-------------------------------------------------------------------------------

Session 19

12:00 NOON - 2:00 PM

Special Purpose Applications
Chair: Kang G. Shin
University of Michigan, Ann Arbor
-------------------------------------------------------------------------------

     Bitonic Sorting on Benes Networks --Beverly M. Gocal and Kenneth E.
     Batcher, Kent State University

     Designing Adaptable Real-Time Fault-Tolerant Parallel Systems --Celio
     Estevan Moron, Universidade Federal de Sao Carlos

     Improving Memory Performance for Indirect Accesses on SIMD Computers
     --James D. Allen and David E. Schimmel, Georgia Institute of Technology

     A New Approach to Pipeline FFT Processor --Shousheng He and Mats
     Torkelson, Lund University

     The Design and Implementation of a SliM Array Processor --Myung H. Sunwoo,
     S. Ong, B. Ahn, and K. Lee, Ajou University, S. Lee, Postech

     Temporal Characterization of Demands for Data Movement on Parallel
     Programs --Bernardo Rodriguez and Harry Jordan, University of Colorado,
     Boulder, Gita Alaghband, University of Colorado, Denver

-------------------------------------------------------------------------------

Session 20

12:00 NOON - 2:00 PM

Communication-III
Chair: Jean-Luc Gaudiot
University of Southern California
-------------------------------------------------------------------------------

     Broadcasting Multiple Messages in the Multiport Model --Amotz Bar-Noy, Tel
     Aviv University and IBM T.J. Watson Research Center, Ching-Tien Ho, IBM
     Almaden Research Center

     The Necessary Conditions for Clos-Type Nonblocking Multicast Networks
     --Yuanyuan Yang, University of Vermont, Burlington, Gerald M. Masson,
     Johns Hopkins University

     A Class of Interconnection Networks for Multicasting --Yuanyuan Yang,
     University of Vermont, Burlington

     Performance Prediction of PVM Programs --Michael R. Steed and Mark J.
     Clement, Brigham Young University

     All-to-All Personalized Exchange in 2D and 3D Tori --Young-Joo Suh and
     Sudhakar Yalamanchili, Georgia Institute of Technology

     Generalized Theory for Deadlock-Free Adaptive Wormhole Routing and its
     Application to Disha Concurrent --Anjan K.V. and Timothy Mark Pinkston,
     University of Southern California, Jose Duato, Universidad Politecnica de
     Valencia

-------------------------------------------------------------------------------

Session 21

12:00 NOON - 2:00 PM

Clusters and Domain Decomposition
Chair: Susamma Barua
California State University, Fullerton
-------------------------------------------------------------------------------

     Efficient Run-time Support for Irregular Task Computations with Mixed
     Granularities --Cong Fu and Tao Yang, University of California, Santa
     Barbara

     A New Technique for 3-D Domain Decomposition on Multicomputers which
     Reduces Message-Passing --Joseph Gil, Israel Institute of Technology, Alan
     Wagner, University of British Columbia

     Application Load Imbalance on Parallel Processors --Vasudha Govindan,
     University of Houston, Mark A. Franklin, Washington University

     Native ATM Application Programmer Interface Testbed for Cluster-Based
     Computing --Patrick W. Dowd, Todd M. Carrozzi, Frank A. Pellegrino, and
     Amy Xin Chen, State University of New York, Buffalo

     SWEB: Towards a Scalable World Wide Web Server on Multicomputers --Daniel
     Andresen, Tao Yang, Vegard Holmedahl, and Oscar H. Ibarra, University of
     California, Santa Barbara

     Parallel Implementations of Irregular Problems Using High-Level Actor
     Language --R.B. Panwar, W. Kim, and G.A. Agha, University of Illinois,
     Urbana-Champaign

-------------------------------------------------------------------------------

Beach Party!!!

-------------------------------------------------------------------------------


                                    LOCATION

The Sheraton Waikiki Hotel is located on the island of Oahu near the city of
Honolulu, the capital of the 50th state Hawaii. Waikiki Beach is located
between downtown Honolulu and Diamond Head in an area which has played a
colorful role in Hawaii's history, and boasts one of the best beaches in the
world!

The Sheraton Waikiki Hotel sits between the beach and Kalakaua Avenue. Next
door is the famous Royal Hawaiian Hotel on land that was the site of the yearly
Makahiki festivals which lasted four months and called for a taboo on war.
Further along the avenue and still fronting the beach is the Moana Surfrider on
land call Ulukou, once the sacred compound of Oahu's highest ranking chiefs.
Across the street at the Sheraton Princess Kaiulani Hotel, there are reminders
of Ainahau, the beautiful gardens and home of Governor A.S. Cleghorn and his
daughter the Princess Kaiulani. This area also invokes the recent history of 
the legendary beach boys and the beginnings of Hawaiian tourism.  The 
accompanying maps reflect the variety in landscape on the island. 
Along with the expected surfing and snorkeling, there are rich opportunities 
for hiking and exploring, and geological, botanical, and historical guided 
tours abound. Some of these Oahu attractions are listed below but every 
first-time traveler is advised to find their own map and guidebook prior 
to arrival.

BISHOP MUSEUM (Honolulu)
BYODO-IN TEMPLE (Kaneohe)
HAWAII OKINAWA CENTER (Waipahu)
HONOLULU BOTANICAL GARDENS
INTERNATIONAL MARKET PLACE
PACIFIC AEROSPACE MUSEUM (Honolulu)
POLYNESIAN CULTURAL CENTER (Laie)
SEA LIFE PARK HAWAII (Waimanalo)
U.S. ARMY MUSEUM OF HAWAII (Honolulu)
WAIKIKI AQUARIUM (Kalakaua Ave)
WAIMEA FALLS PARK (Haleiwa)
WILDLIFE MUSEUM (Honolulu)

AIR TRANSPORT
A host of airlines fly to and through Hawaii. Check travel agents, frequent
flyer offers, and Sunday newspapers for best fares. As with all air travel,
book early to get the best fare.

GROUND TRANSPORT
Several guidebooks advise renting a car based on the fact that there are so
many places to explore. However, one can do without. In that case, expect to
pay around $30 for a taxi from the airport to the hotel. The immediate area is
walkable and there are regular bus routes in Honolulu and bus tours around the
island.

THE SHERATON FAMILY
Along with the IPPS accommodations, the Sheraton Hotels at Waikiki Beach
include The Royal Hawaiian (next door to the Sheraton Waikiki) and the Sheraton
Moana Surfrider (at the head of the beach). Both are elegant reflections of
historic Hawaii and their dining and entertainment facilities can provide a
relaxing change of pace during breaks in symposium events. When you stay at the
Sheraton Waikiki (or the Princess Kaiulani) you can play, dine, and be
entertained at all the Sheraton resorts on Waikiki Beach and Sheraton's golf
resort at Makaha, and just charge it to your room.

The Royal Hawaiian Hotel offers an exciting authentic Hawaiian Luau along
Waikiki Beach on Monday evenings. The Sheraton Polynesian Revue, a dinner show,
is presented nightly at the Sheraton Princess Kaiulani Hotel.

Golfers, organize! The Sheraton Makaha Resort and Country Club will give IPPS
attendees a special rate to play at the Sheraton Makaha West Course. This
applies for a minimum of 4 foursomes, so a sign-up sheet will be available at
registration.

A special family feature for all guests at the Sheraton Hotels in Waikiki is
free child care for children ages 5-12 years, daily from 9 am to 5 pm at the
Children's Center. Child care at other times and for other ages may be arranged
at an hourly fee through a private service, Sitters Unlimited (808-262-5728).

ACCOMMODATIONS
Call 1-800-STAY-ITT (782-9488) and ask for the CIEEE RATE PLAN (for IPPS '96).
As the reservation form cautions, book early ... rooms are in demand!

Symposium events will be held in the Hawaiian Ballroom area of the Sheraton
Waikiki Hotel. Accommodations are available to IPPS attendees at both the
Sheraton Waikiki Hotel and the Sheraton Princess Kaiulani Hotel (1 block away,
across Kalakaua Avenue). The room rates shown below are also listed on the
tearout reservation form in the center of the program. Note that the room rate
is the same for singles and doubles. There is a charge of $25 per night for a
third person for triple adult occupancy and $50 for quad, available only in the
run-of-ocean and run-of-mountain rooms. The Sheraton Family Plan allows parents
to have their children in the same room at no additional charge if the children
are under 18 years of age.

Sheraton Waikiki Run-Of-Ocean Rooms ($185) - Consist of ocean-front and partial
ocean views. The exact mix will not be known until the day of arrival and is
dependent upon availability in each category on the day of arrival.

Sheraton Waikiki Run-Of-Mountain Rooms ($135) - Consist of city and mountain
views, both located on the mountain side of the hotel. The exact mix will not
be known until the day of arrival and is dependent upon availability in each
category on the day of arrival.

Sheraton Waikiki Manor Wing Rooms ($95) - Located in a separate annex of the
main building, without a view. They do not accommodate triple or quad
occupancy.

Princess Kaiulani Run-Of-Main Building Rooms ($115) - Located in three
high-rise towers with views of Waikiki, the ocean or the nearby mountains. The
exact mix will not be known until the day of arrival and is dependent upon
availability in each category on the day of arrival. They do not accommodate
triple or quad occupancy.



          10th INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM (IPPS '96)
                               April 15-19, 1996
                       Sheraton Waikiki, Honolulu, Hawaii

                           Advance Registration Form

Please mail or fax to

 Attn: IPPS 96 Registration
         IEEE Computer Society
         1730 Massachusetts Avenue, NW
         Washington, DC 20036

         Vox : (202) 371 1013
         Fax : (202) 728 0884

PLEASE PRINT:
    Name: ____________________________________________________________________
             Last/Family          First          M.I.           Name on Badge

    Company:_______________________________________________________

    Address/MailStop:_________________________________________________________

    City/State/Zip/Country:___________________________________________________

    Phone (day time):__________________________Fax:______________________

    IEEE/CS Membership Number:__________________E-Mail:________________________

    Do you have any special needs ?___________________________________________

    Do not include my mailing address on: _______Non-Society mailing lists_____Meeting Attendee Lists

PLEASE CIRCLE APPROPRIATE FEES:
    . . . Symposium Registration Fees:

                           Member       Non-Member    Student
Advance Registration       $295         $370          $165
(until March 15, 1996)
Late/On-site Registration  $350         $440          $215
(After March 29 1996)

   . . . Tutorial Registration Fees:(per tutorial)

Advance Registration       $150         $200
(until March 15, 1996)
Late/On-site Registration  $190         $235
(After March 29 1996)

Check Tutorial(s) you wish to attend             Compute payment below

Tuesday April 16
( ) 1. (am) An introduction to the Mess-          Symposium fee      $________
            age Passing Interface

( ) 2. (pm) Parallel and Distributed              Tutorial fee       $________
            Simulation Techniques with
            Applications to VLSI, Multi-
            processor Architectures and
            Mobile Telecommunication
            Systems                        Total Enclosed(in US $)_______

Payment must be enclosed.  Please make cheques payable to IEEE Computer Society
All payments must be in US dollars drawn on a US Bank.

Method of payment:

___Personal Check(No._______________)      ____Company Check(No.______________)
___Travellers checks      ___U.S Government Purchase Order(Original must accompany registration form)

___AMERICAN EXPRESS     ___MASTERCARD     ____VISA       ____DINERS CLUB

Credit card number ____________________          Exp. Date____________
Cardholder Name _____________________________________________________

Signature________________________________

Written requests must be received in the IEEE Computer Society no later than
March 15 1996. Refunds are subject to a $50 processing fee. All no-show registrations
will be billed in full. Registrations after March 29, 1996 will be accepted
on-site only.



            IPPS '96 HOTEL RESERVATION FORM 
        April 15-19, 1996 Sheraton Waikiki Hotel

Special rates available to IPPS attendees

Rate Sheraton Waikiki Hotel
$185 Run-of-Ocean rooms
$135 Run-of-Mountain rooms
$95 Manor Wing (sgl or dbl occupancy only)

Princess Kaiulani Hotel
$115 Run-of-Main (sgl or dbl occupancy only)

Book early, rooms are in demand !!!!!

Reservations must be received by the hotel along with a one night deposit or
credit card guarantee no later than March 15, 1996. Requests received AFTER
March 15, 1996 will be confirmed on a space available basis only.Deposit will
be refunded if reservation is cancelled and notice received at the Hotel thirty
(30) days prior to arrival date.

Room rates are subject to the current 10.17% Hawaii State and Room tax. Where
available, triple occupancy is $25 additional daily; quad is $50 additional.
The family plan allows children under 18 years to stay at no charge in the same
room with parents. Note that IEEE rates listed here apply from April 14 to
April 20 at the Sheraton Waikiki and from April 15 to 20 at the Sheraton
Princess Kaiulani. Should the category you request be sold out, the next best
available will be confirmed.

Check in time is 3:00pm Check out time is 12 noon CALL 1-800-STAY-ITT
(782-9488) AND ASK FOR THE CIEEE RATE PLAN (for IPPS 96)

To make reservations when you contact the hotel, provide the following
information:

1. Full name
2. Arrival and Departure Dates
3. Estimated Time of Arrival and Departure
4. Full Address
5. Phone and Fax number
6. Room type
7. Number of persons in room and ages of children, if any (See family plan for
under age 18)

A one night deposit or credit card guarantee is required

Credit cards accepted
American Express
Carte Blanche
Diners Club
Mastercard
VISA

Make checks payable to Sheraton Waikiki Hotel and write confirmation number on
the check.

Mail to
Group Reservations Dept., Sheraton Waikiki Hotel, 2255 Kalakaua Avenue
Honolulu, Hawaii 96815, USA

-------------------------------------------------------------------------------
Please be sure to record your confirmation number

-------------------------------------------------------------------------------


