Newsgroups: comp.parallel.mpi
From: salo@mrjones.engr.sgi.com (Eric Salo)
Subject: Re: mpi availability & performance
Organization: Silicon Graphics, Inc.  Mountain View, CA
Date: 22 May 1995 16:48:55 GMT
Message-ID: <3pqf9n$sr9@fido.asd.sgi.com>

> Further experience from vendors is that high bandwidth, low latency
> implementations of the MPICH device work quite well.  Nay sayers who
> have shared memory should talk to SGI about their excellent results
> with the power challenge (585mbyte/second bandwidth, approx. 10us latency,
> data left in cache of destination process).

Well...yes and no. There are real benchmarks out there (such as mpptest) that
do report obscenely high bandwidths like this on the Power Challenge, but this
must be taken in context. As Tony has correctly pointed out, message data is
left in the L2 cache of the destination processes after the message is sent.
So, if the sending process does not modify its data before sending it again,
the receiver is able to do a cache-to-cache copy. Alas, this does not happen
particularly frequently in real applications. For uncached data, we're seeing
bandwidths of roughly 60 MB/sec (which is still pretty good).

Eric Salo         Silicon Graphics Inc.             "Do you know what the
(415)390-2998     2011 N. Shoreline Blvd, 7L-802     last Xon said, just
salo@sgi.com      Mountain View, CA   94043-1389     before he died?"

