Newsgroups: comp.parallel.mpi
From: brianmcg@flowbee.interaccess.com (Brian V. McGroarty)
Subject: Managing three dissimilar processors on one bus
Organization: InterAccess, Chicago's best Internet Service Provider
Date: 15 May 1995 05:28:23 GMT
Message-ID: <3p6opn$p3v@nntp.interaccess.com>

I am looking at implementing a message based parallel processing system 
on some interesting hardware; I would appreciate any thoughts on the best 
way to manage it:

This system, a moderately popular console game system, has three completely 
dissimilar processors on a single bus.  The only familiar processor is an 
MC68000; the other two are RISC-based units which, apart from offering 
extra processing power, also manage the display and audio.

One of the RISC processors has a 64-bit bus which is generally accessed 
by the instruction set as a 32-bit bus.  The 64-bit bus exists primarilly 
because the chip also contains video display circuitry and a blitter 
which can access memory 64-bits at a time.  This chip has 4kb of local 
memory and access to the main pool.  Its memory can be accessed externally.

The second RISC processor has a 16-bit bus, but has an almost identical 
instruction set to the first RISC processor, which means operations are 
done with 32-bit registers.  This chip has 8kb local memory and access to 
the main pool.  Internal memory is also available externally.

Neither processor can reliably execute code outside of its internal pool, 
which means that all code must be overlaid.



My intention is to shut off the 68000 as it runs at a considerably lower 
clock-rate than the two RISC processors, thus it doesn't make good use of 
the bus.

This leaves me with two processors with distinctly different 
capabilities; the 64-bit data path to the first RISC processor makes it 
attractive, however the smaller internal memory and the fact that its bus 
is constantly burdened for display purposes counts against it.  


The 16-bit data path of the second processor is restrictive, as is a problem 
with the scoreboarding circuitry which necessitates special coding in 
order to avoid problems when writing to external memory, on the other 
hand the processor is virtually always unburdened, and it has a larger 
internal memory pool.

Given that the first processor is already burdened and doesn't quite have 
the room the second processor does for a generic resource manager, would 
I be wise in arbitrating all resources from the second RISC processor?  How are 
message ports generally arbitrated in a system in which either processor 
might pull a message to dispatch from the same list at any given time?  

My thought is that so long as the first processor can always instantly 
interrupt the second processor to request a new dispatch or to 
allocate/deallocate resources I will have a fairly efficient system as 
far as message-based task dispatching systems go, however is the message 
system the best route when effectively dealing with two processors?  My 
thought is that it is.

The intended use for this system is for the creation of a real-time 3D 
environment for a game.  Generation of an interactive 3D environment can 
be broken up into the actor positioning / interaction, polygon 
transformation and rendering stages.  I would rather not run these 
concurrently as this would mean lagging a frame or two, and the hardware 
is slow enough that this could mean a net 1/8 of a second slack between 
player control and visual response.  For this reason, I intend to 
implement these as separate stages which create commands in the form of 
messages for the coming stages.

Any feedback would be appreciated!
-Brian-

