Newsgroups: comp.os.parix
From: vntavora@eden.dei.uc.pt (Vitor Noronha Tavora)
Subject: [Q]I/O Problem in Parix
Organization: Universidade de Coimbra
Date: 2 Jun 1997 15:21:34 GMT
Message-ID: <5muodu$889@morgana.mat.uc.pt>


I'm using a Parsytec Xplorer with 8 transputer, which is connected to a
Sun Sparc 2 host machine, exclusively dedicated to the Parsytec computer.
I'm experimenting some strange results with I/O, namely, my program which
is running in the 8 processors, performs several simultaneous I/O writes.
I already know that writes are done as a RPC service in the host machine,
a service managed by the host machine D-SERVER, which is certainly a
bottleneck. 
The problem that I'm experimenting is  
According to the manual, the D-SERVER can perfom I/O in two ways:
* Blocking fashion, which the one I thing  I'm using ( the machine
administrator is evasive about this...he probably doesn't know).

* Non-blocking.

Using the blocking way, and using a synchronisation (barrier) right
before the writes (so the processors are all synchronised)  the
eigth writes (one per processor) presents "paired write-times", that is
the write-times are equal for pair of processors. To be more precise,
the time-write are equal for processor 0,4; 1,5; 2,6; 3,7;, increasing
from  pair 0,4 to pair 3,7.
The grid processor are like this:

           -----------------
           | 4 | 5 | 6 | 7 |
           -----------------
------->   | 0 | 1 | 2 | 3 |
|           -----------------
|  
|
-------> Connects to the host machine (Sun Sparc 2)


So I have the following questions:

(1) Are I/O operations (writes in this case) performed in pair, so that
if there are more than one I/O write request, these requests are
performed in group of two ? (Maybe this an exigence of the D-SERVER ? )
If the I/O operations are not performed in pair, why isn't the
write performed by processor 0 the quickiest (since I/O is
performed through processor 0 --acording to the manual--).

(2) And why does the Write operation executed by processor 4 perfoms
*ALWAYS* before than processor 1, even if the 'distance' (processor hop)
of processor 4 to processor 0 is equal to the distance of processor 1 to
processor 0 ( 1 hop each). The same question applies to processor 2
and 5, 3 and 6, respectively  ?

Thanks in advance for any help.

Vitor tavora

PS: Since my news server is frequently down, please answer via e-mail. Thanks.
.


