Newsgroups: comp.parallel.mpi,comp.parallel.pvm,comp.os.parix,comp.realtime,comp.sys.arm
From: D.J.Beckett@ukc.ac.uk (Dave Beckett)
Subject: WoTUG 19 Final Call for Papers - Mar 31-Apr 3 1996, Nottingham, UK
Organization: University of Kent at Canterbury
Date: Fri, 03 Nov 95 16:25:16 GMT
Message-ID: <75@mint.ukc.ac.uk>



                        =====================
                        FINAL CALL FOR PAPERS
                        =====================
                                 
                             WoTUG - 19
                                 
                   March 31st. to April 3rd. 1996

                     Nottingham Trent University


  *** REVISED *** TIMETABLE *** REVISED *** TIMETABLE *** REVISED ***
  *                                                                 *
  *   The date for submission of papers has been relaxed to:        *
  *                                                                 *
  *               Friday, 17th. November, 1995                      *
  *                                                                 *
  *   The rest of the timetable is unchanged.  Author notification: *
  *                                                                 *
  *               Friday, 15th. December, 1995                      *
  *                                                                 *
  *   Camera-ready copy of accepted and revised papers by:          *
  *                                                                 *
  *               Friday, 19th. January, 1996                       *
  *                                                                 *
  *** REVISED *** TIMETABLE *** REVISED *** TIMETABLE *** REVISED ***


BACKGROUND:
-----------

The concept of transputers and transputing has outgrown the
confines of a single manufacturer.  Many companies are marketing
highly parallel systems which to a lesser or greater extent are
following transputer principles.  These principles are relevant to all
types of processing -- from high performance super computing to
single processor micro-controllers in embedded systems.

The transputer principles are:

  o communication is as fundamental as arithmetic and has a cost of
    the same order of magnitude;
     
  o parallelism is as fundamental as looping for structuring designs
    and has a cost of the same order of magnitude.

It is proving difficult to build efficient high-performance
computer systems simply by taking very fast processors and joining them
together with very high bandwidth interconnect.  Apart from the need to
keep the computational and communication power in balance, it is also
essential to reduce communication start-up costs (in line with
increasing bandwidth) and to reduce process context-switch time (in
line with increasing computational power).  Failure in either of these
regards leads to coarse-grained parallelism, which results in
insufficient parallel slackness to allow efficient use of individual
processing nodes, potentially serious cache-coherency problems for
super-computing applications and unnecessarily large worst-case latency
guarantees for real-time applications.

Transputer principles impose no constraints on the granularity of
process and communication.  They give us the chance to design systems
the ways the problems demand and produce implementations that scale
efficiently in line with problem size and processor/communication
resource.  They are certainly worth checking out.

The novel angle recently demonstrated is that it has become possible to
transfer these ideas efficiently on to many other architectures --
creating virtual transputers.


INVITATION:
-----------

Papers reporting experiences of using, developing and supporting
transputer principles are invited for submission to WoTUG-19, the
19th. Technical Conference of the World occam and Transputer User
Group.  The following guidelines are offered but provide a
non-exhaustive list:

  o software support for transputer principles: environments,
    CASE design tools and rule-checkers; debuggers and other analysis
    tools; Bulk Synchronous Parallelism (BSP) implementations;
    retargeted or portable occam compilers; language issues.

  o hardware support for transputer principles: routing devices
    and other interconnect strategies; Virtual Channel Processor
    implementations (T9000 and others ...); new transputer-like
    processors and interconnect technologies -- e.g. the ST20-450
    (an upgraded T425) and the IEEE Draft Standard P1355 for
    Heterogeneous InterConnect (DS-links); other multi-processor
    architectures (current and proposed).

  o application of transputer principles: real-time control;
    safety-critical; super-computing; modelling; simulation;
    engineering; databases; information systems; tele-communications;
    consumer products; games; other ....

  o theory: CSP, CCS, BSP, rigorous design methods, ...

  o education and training: what are we teaching, should we be
    teaching it, how painful is it, ... ?


PROGRAMME COMMITTEE:
--------------------

All submissions will be refereed.  The programme committee will consist
of the current WoTUG Committee augmented by:

  Professor David May (Univerity of Bristol, England)
  Professor Dyke Stiles (Utah State University, USA)
  Dr. Brian O'Neil (Nottingham Trent University, England)
  Dr. Patrick A. Nixon (University of Dublin, Ireland)

The current WoTUG Committee may be found on:

  <URL:http://www.hensa.ac.uk/parallel/groups/wotug/committee.doc>

  <URL:ftp://unix.hensa.ac.uk/pub/parallel/groups/wotug/committee.doc>


IMPORTANT DATES:
----------------

Four copies of original papers, in English, of no more than 16 pages
should be submitted by 17th November 1995 to :

  Dr B.C. O'Neill
  Department of Electrical and Electronic Engineering
  Nottingham Trent University
  Burton Street
  Nottingham
  NG1 4BU

  tel:   +44 115 941 8418  ext. 2095 (secretary: ext. 2799)
  tax:   +44 115 948 6567
  email: eee3oneilbc@ntu.ac.uk

Electronic submission of uuencoded compressed PostScript (one copy)
to the above email address is also acceptable, but authors should
ensure they receive confirmation of such submission.

Authors will be notified of the acceptance of their papers by
15th December 1995.

Camera ready copy of selected papers will be required by January
19th., 1996.

All accepted papers will be published in the Conference Proceedings
by IOS Press as part of their Concurrent Systems Engineering series.

Further information about this conference will be updated on:

  <URL:http://www.hensa.ac.uk/parallel/groups/wotug/wotug19/>

  <URL:ftp://unix.hensa.ac.uk/pub/parallel/groups/wotug/wotug19/>

_______________________________
* all trademarks and registered names are acknowledged

