Newsgroups: comp.os.parix
From: schumanm@Informatik.TU-Muenchen.DE (Matthias Schumann)
Subject: fat tree topology of GC/PowerPlus-64
Organization: Technische Universitaet Muenchen, Germany
Date: 23 Jun 1994 07:43:40 GMT
Message-ID: <2ubefc$qen@hpsystem1.informatik.tu-muenchen.de>

Hi there,

I have just gone through a Parystec advertising paper and found the following 
description of the GC/PowerPlus-64 system configuration:

32 nodes with 2 processors per node and a total memory of 2 GB
4x8 "Fat Grid" topology

I know about the "Fat Tree" topology, but I have never heard of a "Fat Grid"
topology. OK, it's not PARIX-OS related, but maybe anyone out there can give 
a hint on "Fat Grids" ?!

And a PARIX related topic: the PowerPlus architectures use a PowerPC as
application processor and a transputer as message processor. If there is 
a message arriving for the PowerPC the transputer has to notify the 
PowerPC and vice versa the PowerPC has to notify the transputer when
there is a send request. Thus, I am interested how this is implemented 
within PARIX. Are interrupts used, do the processors poll on semaphores
(what should be crucial to performance since the transputer has no cache
and therefore there is no common cache consitency protocol to implement cached
semaphores), or does PARIX check for message traffic during the clock-tick 
interrupt ?

Ciao,
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| Matthias Schumann                        Department of Computer Science/SAB |
| schumanm@informatik.tu-muenchen.de                              TU-Muenchen |
| Phone: +49 89 2105 2684                                      80290 Muenchen |
 
 


